4e73238d16
The interrupt enable bit for the performance counters is in the Control
Register $24, not in the counter register.
loongson2_perfcount_handler(), we need to use
Reported-by: Xu Hengyang <hengyang@mail.ustc.edu.cn>
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/1198/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
|
||
|---|---|---|
| .. | ||
| Makefile | ||
| common.c | ||
| op_impl.h | ||
| op_model_loongson2.c | ||
| op_model_mipsxx.c | ||
| op_model_rm9000.c | ||