83b73d6cb8
Add code to manage the context's of the ColdFire V4e MMU. This code is mostly taken from the Freescale 2.6.35 kernel BSP for MMU enabled ColdFire. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
327 lines
7.2 KiB
C
327 lines
7.2 KiB
C
#ifndef __M68K_MMU_CONTEXT_H
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#define __M68K_MMU_CONTEXT_H
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#include <asm-generic/mm_hooks.h>
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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#ifdef CONFIG_MMU
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#if defined(CONFIG_COLDFIRE)
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#include <asm/atomic.h>
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#include <asm/bitops.h>
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#include <asm/mcfmmu.h>
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#include <asm/mmu.h>
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#define NO_CONTEXT 256
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#define LAST_CONTEXT 255
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#define FIRST_CONTEXT 1
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extern unsigned long context_map[];
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extern mm_context_t next_mmu_context;
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extern atomic_t nr_free_contexts;
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extern struct mm_struct *context_mm[LAST_CONTEXT+1];
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extern void steal_context(void);
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static inline void get_mmu_context(struct mm_struct *mm)
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{
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mm_context_t ctx;
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if (mm->context != NO_CONTEXT)
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return;
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while (atomic_dec_and_test_lt(&nr_free_contexts)) {
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atomic_inc(&nr_free_contexts);
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steal_context();
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}
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ctx = next_mmu_context;
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while (test_and_set_bit(ctx, context_map)) {
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ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
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if (ctx > LAST_CONTEXT)
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ctx = 0;
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}
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next_mmu_context = (ctx + 1) & LAST_CONTEXT;
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mm->context = ctx;
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context_mm[ctx] = mm;
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}
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/*
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* Set up the context for a new address space.
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*/
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#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0)
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/*
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* We're finished using the context for an address space.
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*/
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static inline void destroy_context(struct mm_struct *mm)
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{
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if (mm->context != NO_CONTEXT) {
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clear_bit(mm->context, context_map);
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mm->context = NO_CONTEXT;
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atomic_inc(&nr_free_contexts);
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}
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}
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static inline void set_context(mm_context_t context, pgd_t *pgd)
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{
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__asm__ __volatile__ ("movec %0,%%asid" : : "d" (context));
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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get_mmu_context(tsk->mm);
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set_context(tsk->mm->context, next->pgd);
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}
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/*
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* After we have set current->mm to a new value, this activates
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* the context for the new mm so we see the new mappings.
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*/
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static inline void activate_mm(struct mm_struct *active_mm,
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struct mm_struct *mm)
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{
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get_mmu_context(mm);
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set_context(mm->context, mm->pgd);
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}
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#define deactivate_mm(tsk, mm) do { } while (0)
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extern void mmu_context_init(void);
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#define prepare_arch_switch(next) load_ksp_mmu(next)
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static inline void load_ksp_mmu(struct task_struct *task)
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{
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unsigned long flags;
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struct mm_struct *mm;
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int asid;
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pgd_t *pgd;
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pmd_t *pmd;
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pte_t *pte;
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unsigned long mmuar;
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local_irq_save(flags);
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mmuar = task->thread.ksp;
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/* Search for a valid TLB entry, if one is found, don't remap */
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mmu_write(MMUAR, mmuar);
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mmu_write(MMUOR, MMUOR_STLB | MMUOR_ADR);
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if (mmu_read(MMUSR) & MMUSR_HIT)
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goto end;
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if (mmuar >= PAGE_OFFSET) {
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mm = &init_mm;
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} else {
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pr_info("load_ksp_mmu: non-kernel mm found: 0x%p\n", task->mm);
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mm = task->mm;
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}
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if (!mm)
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goto bug;
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pgd = pgd_offset(mm, mmuar);
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if (pgd_none(*pgd))
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goto bug;
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pmd = pmd_offset(pgd, mmuar);
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if (pmd_none(*pmd))
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goto bug;
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pte = (mmuar >= PAGE_OFFSET) ? pte_offset_kernel(pmd, mmuar)
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: pte_offset_map(pmd, mmuar);
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if (pte_none(*pte) || !pte_present(*pte))
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goto bug;
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set_pte(pte, pte_mkyoung(*pte));
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asid = mm->context & 0xff;
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if (!pte_dirty(*pte) && mmuar <= PAGE_OFFSET)
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set_pte(pte, pte_wrprotect(*pte));
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mmu_write(MMUTR, (mmuar & PAGE_MASK) | (asid << MMUTR_IDN) |
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(((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK)
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>> CF_PAGE_MMUTR_SHIFT) | MMUTR_V);
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mmu_write(MMUDR, (pte_val(*pte) & PAGE_MASK) |
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((pte->pte) & CF_PAGE_MMUDR_MASK) | MMUDR_SZ_8KB | MMUDR_X);
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mmu_write(MMUOR, MMUOR_ACC | MMUOR_UAA);
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goto end;
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bug:
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pr_info("ksp load failed: mm=0x%p ksp=0x08%lx\n", mm, mmuar);
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end:
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local_irq_restore(flags);
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}
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#elif defined(CONFIG_SUN3)
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#include <asm/sun3mmu.h>
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#include <linux/sched.h>
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extern unsigned long get_free_context(struct mm_struct *mm);
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extern void clear_context(unsigned long context);
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/* set the context for a new task to unmapped */
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static inline int init_new_context(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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mm->context = SUN3_INVALID_CONTEXT;
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return 0;
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}
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/* find the context given to this process, and if it hasn't already
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got one, go get one for it. */
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static inline void get_mmu_context(struct mm_struct *mm)
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{
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if (mm->context == SUN3_INVALID_CONTEXT)
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mm->context = get_free_context(mm);
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}
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/* flush context if allocated... */
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static inline void destroy_context(struct mm_struct *mm)
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{
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if (mm->context != SUN3_INVALID_CONTEXT)
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clear_context(mm->context);
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}
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static inline void activate_context(struct mm_struct *mm)
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{
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get_mmu_context(mm);
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sun3_put_context(mm->context);
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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activate_context(tsk->mm);
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}
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#define deactivate_mm(tsk, mm) do { } while (0)
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static inline void activate_mm(struct mm_struct *prev_mm,
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struct mm_struct *next_mm)
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{
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activate_context(next_mm);
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}
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#else
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#include <asm/setup.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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static inline int init_new_context(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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mm->context = virt_to_phys(mm->pgd);
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return 0;
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}
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#define destroy_context(mm) do { } while(0)
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static inline void switch_mm_0230(struct mm_struct *mm)
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{
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unsigned long crp[2] = {
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0x80000000 | _PAGE_TABLE, mm->context
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};
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unsigned long tmp;
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asm volatile (".chip 68030");
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/* flush MC68030/MC68020 caches (they are virtually addressed) */
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asm volatile (
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"movec %%cacr,%0;"
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"orw %1,%0; "
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"movec %0,%%cacr"
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: "=d" (tmp) : "di" (FLUSH_I_AND_D));
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/* Switch the root pointer. For a 030-only kernel,
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* avoid flushing the whole ATC, we only need to
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* flush the user entries. The 68851 does this by
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* itself. Avoid a runtime check here.
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*/
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asm volatile (
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#ifdef CPU_M68030_ONLY
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"pmovefd %0,%%crp; "
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"pflush #0,#4"
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#else
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"pmove %0,%%crp"
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#endif
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: : "m" (crp[0]));
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asm volatile (".chip 68k");
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}
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static inline void switch_mm_0460(struct mm_struct *mm)
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{
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asm volatile (".chip 68040");
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/* flush address translation cache (user entries) */
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asm volatile ("pflushan");
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/* switch the root pointer */
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asm volatile ("movec %0,%%urp" : : "r" (mm->context));
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if (CPU_IS_060) {
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unsigned long tmp;
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/* clear user entries in the branch cache */
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asm volatile (
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"movec %%cacr,%0; "
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"orl %1,%0; "
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"movec %0,%%cacr"
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: "=d" (tmp): "di" (0x00200000));
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}
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asm volatile (".chip 68k");
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)
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{
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if (prev != next) {
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if (CPU_IS_020_OR_030)
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switch_mm_0230(next);
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else
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switch_mm_0460(next);
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}
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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static inline void activate_mm(struct mm_struct *prev_mm,
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struct mm_struct *next_mm)
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{
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next_mm->context = virt_to_phys(next_mm->pgd);
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if (CPU_IS_020_OR_030)
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switch_mm_0230(next_mm);
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else
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switch_mm_0460(next_mm);
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}
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#endif
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#else /* !CONFIG_MMU */
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static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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return 0;
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)
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{
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}
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#define destroy_context(mm) do { } while (0)
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#define deactivate_mm(tsk,mm) do { } while (0)
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static inline void activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm)
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{
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}
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#endif /* CONFIG_MMU */
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#endif /* __M68K_MMU_CONTEXT_H */
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