fb702b942b
This model is based on the on-chip interrupt model used by the TILE-Gx next-generation hardware, and interacts much more cleanly with the Linux generic IRQ layer. The change includes modifications to the Tilera hypervisor, which are reflected in the hypervisor headers in arch/tile/include/arch/. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
87 lines
3.1 KiB
C
87 lines
3.1 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_IRQ_H
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#define _ASM_TILE_IRQ_H
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#include <linux/hardirq.h>
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/* The hypervisor interface provides 32 IRQs. */
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#define NR_IRQS 32
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/* IRQ numbers used for linux IPIs. */
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#define IRQ_RESCHEDULE 1
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void ack_bad_irq(unsigned int irq);
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/*
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* Different ways of handling interrupts. Tile interrupts are always
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* per-cpu; there is no global interrupt controller to implement
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* enable/disable. Most onboard devices can send their interrupts to
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* many tiles at the same time, and Tile-specific drivers know how to
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* deal with this.
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*
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* However, generic devices (usually PCIE based, sometimes GPIO)
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* expect that interrupts will fire on a single core at a time and
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* that the irq can be enabled or disabled from any core at any time.
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* We implement this by directing such interrupts to a single core.
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*
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* One added wrinkle is that PCI interrupts can be either
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* hardware-cleared (legacy interrupts) or software cleared (MSI).
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* Other generic device systems (GPIO) are always software-cleared.
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*
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* The enums below are used by drivers for onboard devices, including
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* the internals of PCI root complex and GPIO. They allow the driver
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* to tell the generic irq code what kind of interrupt is mapped to a
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* particular IRQ number.
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*/
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enum {
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/* per-cpu interrupt; use enable/disable_percpu_irq() to mask */
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TILE_IRQ_PERCPU,
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/* global interrupt, hardware responsible for clearing. */
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TILE_IRQ_HW_CLEAR,
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/* global interrupt, software responsible for clearing. */
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TILE_IRQ_SW_CLEAR,
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};
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/*
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* Paravirtualized drivers should call this when they dynamically
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* allocate a new IRQ or discover an IRQ that was pre-allocated by the
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* hypervisor for use with their particular device. This gives the
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* IRQ subsystem an opportunity to do interrupt-type-specific
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* initialization.
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*
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* ISSUE: We should modify this API so that registering anything
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* except percpu interrupts also requires providing callback methods
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* for enabling and disabling the interrupt. This would allow the
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* generic IRQ code to proxy enable/disable_irq() calls back into the
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* PCI subsystem, which in turn could enable or disable the interrupt
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* at the PCI shim.
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*/
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void tile_irq_activate(unsigned int irq, int tile_irq_type);
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/*
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* For onboard, non-PCI (e.g. TILE_IRQ_PERCPU) devices, drivers know
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* how to use enable/disable_percpu_irq() to manage interrupts on each
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* core. We can't use the generic enable/disable_irq() because they
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* use a single reference count per irq, rather than per cpu per irq.
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*/
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void enable_percpu_irq(unsigned int irq);
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void disable_percpu_irq(unsigned int irq);
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void setup_irq_regs(void);
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#endif /* _ASM_TILE_IRQ_H */
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