5698bd28c6
Ensure the CPLD 8bit settings are preserved over a suspend/resume cycle as the CPU sends a hard-reset at resume time. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
30 lines
824 B
C
30 lines
824 B
C
/* linux/include/asm-arm/arch-s3c2410/osiris-cpld.h
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*
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* Copyright 2005 Simtec Electronics
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* http://www.simtec.co.uk/products/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* OSIRIS - CPLD control constants
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_OSIRISCPLD_H
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#define __ASM_ARCH_OSIRISCPLD_H
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/* CTRL0 - NAND WP control */
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#define OSIRIS_CTRL0_NANDSEL (0x3)
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#define OSIRIS_CTRL0_BOOT_INT (1<<3)
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#define OSIRIS_CTRL0_PCMCIA (1<<4)
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#define OSIRIS_CTRL0_FIX8 (1<<5)
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#define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6)
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#define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7)
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#define OSIRIS_CTRL1_FIX8 (1<<0)
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#define OSIRIS_ID_REVMASK (0x7)
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#endif /* __ASM_ARCH_OSIRISCPLD_H */
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