c53c9cf60e
Add core support for the Kendin/Micrel KS8695 processor family. It is an ARM922-T based SoC with integrated USART, 4-port Ethernet Switch, WAN Ethernet port, and optional PCI Host bridge, etc. http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp This patch is based on earlier patches from Lennert Buytenhek, Ben Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in March 2006; and Micrel's 2.6.9 port. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
65 lines
2.7 KiB
C
65 lines
2.7 KiB
C
/*
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* include/asm-arm/arch-ks8695/regs-wan.h
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*
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* Copyright (C) 2006 Andrew Victor
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*
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* KS8695 - WAN Registers and bit definitions.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef KS8695_WAN_H
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#define KS8695_WAN_H
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#define KS8695_WAN_OFFSET (0xF0000 + 0x6000)
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#define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET)
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#define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET)
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/*
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* WAN registers
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*/
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#define KS8695_WMDTXC (0x00) /* DMA Transmit Control */
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#define KS8695_WMDRXC (0x04) /* DMA Receive Control */
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#define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */
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#define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */
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#define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */
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#define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */
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#define KS8695_WMAL (0x18) /* MAC Station Address Low */
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#define KS8695_WMAH (0x1c) /* MAC Station Address High */
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#define KS8695_WMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */
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#define KS8695_WMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */
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/* DMA Transmit Control Register */
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#define WMDTXC_WMTRST (1 << 31) /* Soft Reset */
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#define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */
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#define WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */
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#define WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */
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#define WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */
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#define WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */
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#define WMDTXC_WMTLB (1 << 8) /* Loopback mode */
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#define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */
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#define WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */
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#define WMDTXC_WMTE (1 << 0) /* TX Enable */
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/* DMA Receive Control Register */
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#define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */
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#define WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */
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#define WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */
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#define WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */
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#define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */
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#define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */
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#define WMDRXC_WMRM (1 << 5) /* Receive Multicast */
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#define WMDRXC_WMRU (1 << 4) /* Receive Unicast */
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#define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */
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#define WMDRXC_WMRA (1 << 2) /* Receive All */
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#define WMDRXC_WMRE (1 << 0) /* RX Enable */
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/* Additional Station Address High */
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#define WMAAH_E (1 << 31) /* Address Enabled */
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#endif
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