285f5fa7e9
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
26 lines
704 B
ArmAsm
26 lines
704 B
ArmAsm
/*
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* include/asm-arm/arch-iop13xx/debug-macro.S
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*
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* Debugging macro include header
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*
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* Copyright (C) 1994-1999 Russell King
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* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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.macro addruart, rx
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mrc p15, 0, \rx, c1, c0
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tst \rx, #1 @ mmu enabled?
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moveq \rx, #0xff000000 @ physical
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orreq \rx, \rx, #0x00d80000
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movne \rx, #0xfe000000 @ virtual
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orrne \rx, \rx, #0x00e80000
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orr \rx, \rx, #0x00002300
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orr \rx, \rx, #0x00000040
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.endm
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#define UART_SHIFT 2
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#include <asm/hardware/debug-8250.S>
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