1643accdaa
The OCTEON II SOC has USB EHCI and OHCI controllers connected directly to the internal I/O bus. This patch adds the necessary 'glue' logic to allow ehci-hcd and ohci-hcd drivers to work on OCTEON II. The OCTEON normally runs big-endian, and the ehci/ohci internal registers have host endianness, so we need to select USB_EHCI_BIG_ENDIAN_MMIO. The ehci and ohci blocks share a common clocking and PHY infrastructure. Initialization of the host controller and PHY clocks is common between the two and is factored out into the octeon2-common.c file. Setting of USB_ARCH_HAS_OHCI and USB_ARCH_HAS_EHCI is done in arch/mips/Kconfig in a following patch. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-usb@vger.kernel.org To: dbrownell@users.sourceforge.net Patchwork: http://patchwork.linux-mips.org/patch/1675/ Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
214 lines
4.3 KiB
C
214 lines
4.3 KiB
C
/*
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* EHCI HCD glue for Cavium Octeon II SOCs.
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*
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* Loosely based on ehci-au1xxx.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2010 Cavium Networks
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*
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*/
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#include <linux/platform_device.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-uctlx-defs.h>
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#define OCTEON_OHCI_HCD_NAME "octeon-ohci"
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/* Common clock init code. */
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void octeon2_usb_clocks_start(void);
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void octeon2_usb_clocks_stop(void);
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static void ohci_octeon_hw_start(void)
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{
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union cvmx_uctlx_ohci_ctl ohci_ctl;
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octeon2_usb_clocks_start();
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ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
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ohci_ctl.s.l2c_addr_msb = 0;
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ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
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ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
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cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
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}
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static void ohci_octeon_hw_stop(void)
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{
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/* Undo ohci_octeon_start() */
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octeon2_usb_clocks_stop();
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}
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static int __devinit ohci_octeon_start(struct usb_hcd *hcd)
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{
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struct ohci_hcd *ohci = hcd_to_ohci(hcd);
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int ret;
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ret = ohci_init(ohci);
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if (ret < 0)
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return ret;
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ret = ohci_run(ohci);
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if (ret < 0) {
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ohci_err(ohci, "can't start %s", hcd->self.bus_name);
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ohci_stop(hcd);
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return ret;
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}
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return 0;
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}
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static const struct hc_driver ohci_octeon_hc_driver = {
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.description = hcd_name,
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.product_desc = "Octeon OHCI",
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.hcd_priv_size = sizeof(struct ohci_hcd),
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/*
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* generic hardware linkage
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*/
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.irq = ohci_irq,
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.flags = HCD_USB11 | HCD_MEMORY,
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/*
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* basic lifecycle operations
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*/
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.start = ohci_octeon_start,
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.stop = ohci_stop,
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.shutdown = ohci_shutdown,
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/*
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* managing i/o requests and associated device resources
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*/
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.urb_enqueue = ohci_urb_enqueue,
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.urb_dequeue = ohci_urb_dequeue,
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.endpoint_disable = ohci_endpoint_disable,
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/*
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* scheduling support
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*/
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.get_frame_number = ohci_get_frame,
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/*
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* root hub support
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*/
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.hub_status_data = ohci_hub_status_data,
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.hub_control = ohci_hub_control,
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.start_port_reset = ohci_start_port_reset,
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};
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static int ohci_octeon_drv_probe(struct platform_device *pdev)
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{
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struct usb_hcd *hcd;
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struct ohci_hcd *ohci;
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void *reg_base;
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struct resource *res_mem;
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int irq;
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int ret;
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if (usb_disabled())
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return -ENODEV;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "No irq assigned\n");
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return -ENODEV;
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}
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res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res_mem == NULL) {
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dev_err(&pdev->dev, "No register space assigned\n");
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return -ENODEV;
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}
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/* Ohci is a 32-bit device. */
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pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
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pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
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hcd = usb_create_hcd(&ohci_octeon_hc_driver, &pdev->dev, "octeon");
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if (!hcd)
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return -ENOMEM;
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hcd->rsrc_start = res_mem->start;
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hcd->rsrc_len = res_mem->end - res_mem->start + 1;
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if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
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OCTEON_OHCI_HCD_NAME)) {
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dev_err(&pdev->dev, "request_mem_region failed\n");
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ret = -EBUSY;
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goto err1;
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}
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reg_base = ioremap(hcd->rsrc_start, hcd->rsrc_len);
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if (!reg_base) {
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dev_err(&pdev->dev, "ioremap failed\n");
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ret = -ENOMEM;
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goto err2;
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}
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ohci_octeon_hw_start();
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hcd->regs = reg_base;
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ohci = hcd_to_ohci(hcd);
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/* Octeon OHCI matches CPU endianness. */
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#ifdef __BIG_ENDIAN
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ohci->flags |= OHCI_QUIRK_BE_MMIO;
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#endif
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ohci_hcd_init(ohci);
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ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
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if (ret) {
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dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
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goto err3;
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}
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platform_set_drvdata(pdev, hcd);
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return 0;
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err3:
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ohci_octeon_hw_stop();
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iounmap(hcd->regs);
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err2:
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release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
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err1:
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usb_put_hcd(hcd);
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return ret;
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}
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static int ohci_octeon_drv_remove(struct platform_device *pdev)
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{
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struct usb_hcd *hcd = platform_get_drvdata(pdev);
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usb_remove_hcd(hcd);
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ohci_octeon_hw_stop();
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iounmap(hcd->regs);
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release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
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usb_put_hcd(hcd);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver ohci_octeon_driver = {
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.probe = ohci_octeon_drv_probe,
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.remove = ohci_octeon_drv_remove,
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.shutdown = usb_hcd_platform_shutdown,
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.driver = {
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.name = OCTEON_OHCI_HCD_NAME,
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.owner = THIS_MODULE,
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}
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};
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MODULE_ALIAS("platform:" OCTEON_OHCI_HCD_NAME);
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