3dfa877367
The new e500mc core from Freescale is based on the e500v2 but with the following changes: * Supports only the Enhanced Debug Architecture (DSRR0/1, etc) * Floating Point * No SPE * Supports lwsync * Doorbell Exceptions * Hypervisor * Cache line size is now 64-bytes (e500v1/v2 have a 32-byte cache line) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
#ifndef _ASM_POWERPC_CACHE_H
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#define _ASM_POWERPC_CACHE_H
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#ifdef __KERNEL__
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/* bytes per L1 cache line */
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#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
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#define L1_CACHE_SHIFT 4
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#define MAX_COPY_PREFETCH 1
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#elif defined(CONFIG_PPC_E500MC)
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#define L1_CACHE_SHIFT 6
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#define MAX_COPY_PREFETCH 4
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#elif defined(CONFIG_PPC32)
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#define L1_CACHE_SHIFT 5
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#define MAX_COPY_PREFETCH 4
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#else /* CONFIG_PPC64 */
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#define L1_CACHE_SHIFT 7
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#endif
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
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struct ppc64_caches {
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u32 dsize; /* L1 d-cache size */
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u32 dline_size; /* L1 d-cache line size */
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u32 log_dline_size;
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u32 dlines_per_page;
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u32 isize; /* L1 i-cache size */
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u32 iline_size; /* L1 i-cache line size */
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u32 log_iline_size;
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u32 ilines_per_page;
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};
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extern struct ppc64_caches ppc64_caches;
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#endif /* __powerpc64__ && ! __ASSEMBLY__ */
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#if !defined(__ASSEMBLY__)
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#define __read_mostly __attribute__((__section__(".data.read_mostly")))
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_CACHE_H */
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