b7dcf7fe7c
Fix problems with the 528x ColdFire CPU cache setup. Do not cache the flash region (if present), and make the runtime settings consistent with the init setting. Problems pointed out by Bernd Buttner <b.buettner@mkc-gmbh.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
150 lines
4.4 KiB
C
150 lines
4.4 KiB
C
/****************************************************************************/
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/*
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* mcfcache.h -- ColdFire CPU cache support code
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*
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* (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com>
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*/
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/****************************************************************************/
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#ifndef __M68KNOMMU_MCFCACHE_H
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#define __M68KNOMMU_MCFCACHE_H
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/****************************************************************************/
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/*
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* The different ColdFire families have different cache arrangments.
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* Everything from a small instruction only cache, to configurable
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* data and/or instruction cache, to unified instruction/data, to
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* harvard style separate instruction and data caches.
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*/
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
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/*
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* Simple version 2 core cache. These have instruction cache only,
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* we just need to invalidate it and enable it.
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*/
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.macro CACHE_ENABLE
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movel #0x01000000,%d0 /* invalidate cache cmd */
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movec %d0,%CACR /* do invalidate cache */
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movel #0x80000100,%d0 /* setup cache mask */
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movec %d0,%CACR /* enable cache */
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.endm
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#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
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#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
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/*
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* New version 2 cores have a configurable split cache arrangement.
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* For now I am just enabling instruction cache - but ultimately I
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* think a split instruction/data cache would be better.
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*/
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.macro CACHE_ENABLE
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movel #0x01400000,%d0
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movec %d0,%CACR /* invalidate cache */
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nop
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movel #0x0000c000,%d0 /* set SDRAM cached only */
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movec %d0,%ACR0
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movel #0x00000000,%d0 /* no other regions cached */
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movec %d0,%ACR1
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movel #0x80400100,%d0 /* configure cache */
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movec %d0,%CACR /* enable cache */
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nop
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.endm
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#endif /* CONFIG_M523x || CONFIG_M527x */
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#if defined(CONFIG_M528x)
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.macro CACHE_ENABLE
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nop
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movel #0x01000000, %d0
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movec %d0, %CACR /* Invalidate cache */
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nop
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movel #0x0000c020, %d0 /* Set SDRAM cached only */
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movec %d0, %ACR0
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movel #0x00000000, %d0 /* No other regions cached */
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movec %d0, %ACR1
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movel #0x80000200, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Enable cache */
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nop
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.endm
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#endif /* CONFIG_M528x */
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#if defined(CONFIG_M5249) || defined(CONFIG_M5307)
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/*
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* The version 3 core cache. Oddly enough the version 2 core 5249
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* has the same SDRAM and cache setup as the version 3 cores.
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* This is a single unified instruction/data cache.
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*/
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.macro CACHE_ENABLE
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movel #0x01000000,%d0 /* invalidate whole cache */
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movec %d0,%CACR
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nop
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#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3)
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movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
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#else
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movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */
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#endif
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movec %d0,%ACR0
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movel #0x00000000,%d0 /* no other regions cached */
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movec %d0,%ACR1
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movel #0xa0000200,%d0 /* enable cache */
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movec %d0,%CACR
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nop
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.endm
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#endif /* CONFIG_M5249 || CONFIG_M5307 */
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#if defined(CONFIG_M532x)
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.macro CACHE_ENABLE
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movel #0x01000000,%d0 /* invalidate cache cmd */
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movec %d0,%CACR /* do invalidate cache */
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nop
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movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */
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movec %d0,%ACR0
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movel #0x00000000,%d0 /* no other regions cached */
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movec %d0,%ACR1
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movel #0x80000200,%d0 /* setup cache mask */
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movec %d0,%CACR /* enable cache */
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nop
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.endm
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#endif /* CONFIG_M532x */
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#if defined(CONFIG_M5407)
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/*
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* Version 4 cores have a true harvard style separate instruction
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* and data cache. Invalidate and enable cache, also enable write
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* buffers and branch accelerator.
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*/
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.macro CACHE_ENABLE
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movel #0x01040100,%d0 /* invalidate whole cache */
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movec %d0,%CACR
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nop
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movel #0x000fc000,%d0 /* set SDRAM cached only */
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movec %d0, %ACR0
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movel #0x00000000,%d0 /* no other regions cached */
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movec %d0, %ACR1
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movel #0x000fc000,%d0 /* set SDRAM cached only */
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movec %d0, %ACR2
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movel #0x00000000,%d0 /* no other regions cached */
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movec %d0, %ACR3
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movel #0xb6088400,%d0 /* enable caches */
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movec %d0,%CACR
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nop
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.endm
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#endif /* CONFIG_M5407 */
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#if defined(CONFIG_M520x)
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.macro CACHE_ENABLE
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move.l #0x01000000,%d0 /* invalidate whole cache */
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movec %d0,%CACR
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nop
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move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
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movec %d0,%ACR0
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move.l #0x00000000,%d0 /* no other regions cached */
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movec %d0,%ACR1
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move.l #0x80400000,%d0 /* enable 8K instruction cache */
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movec %d0,%CACR
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nop
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.endm
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#endif /* CONFIG_M520x */
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/****************************************************************************/
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#endif /* __M68KNOMMU_MCFCACHE_H */
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