1014c22e42
Or we will get things like this when we remove the implicit path: drivers/ssb/embedded.c:32: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' drivers/ssb/driver_chipcommon.c:432: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' drivers/ssb/driver_chipcommon_pmu.c:607: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' drivers/ssb/pcihost_wrapper.c:120: error: ‘THIS_MODULE’ undeclared (first use in this function) drivers/ssb/driver_pcicore.c:721: warning: type defaults to ‘int’ in declaration of ‘EXPORT_SYMBOL’ drivers/ssb/driver_gige.c:249: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
722 lines
18 KiB
C
722 lines
18 KiB
C
/*
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* Sonics Silicon Backplane
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* Broadcom PCI-core driver
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include <linux/ssb/ssb.h>
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#include <linux/pci.h>
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#include <linux/export.h>
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#include <linux/delay.h>
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#include <linux/ssb/ssb_embedded.h>
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#include "ssb_private.h"
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static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
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static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
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static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
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static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
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u8 address, u16 data);
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static inline
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u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
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{
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return ssb_read32(pc->dev, offset);
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}
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static inline
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void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
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{
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ssb_write32(pc->dev, offset, value);
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}
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static inline
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u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
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{
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return ssb_read16(pc->dev, offset);
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}
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static inline
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void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
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{
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ssb_write16(pc->dev, offset, value);
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}
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/**************************************************
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* Code for hostmode operation.
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**************************************************/
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#ifdef CONFIG_SSB_PCICORE_HOSTMODE
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#include <asm/paccess.h>
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/* Probe a 32bit value on the bus and catch bus exceptions.
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* Returns nonzero on a bus exception.
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* This is MIPS specific */
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#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
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/* Assume one-hot slot wiring */
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#define SSB_PCI_SLOT_MAX 16
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/* Global lock is OK, as we won't have more than one extpci anyway. */
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static DEFINE_SPINLOCK(cfgspace_lock);
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/* Core to access the external PCI config space. Can only have one. */
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static struct ssb_pcicore *extpci_core;
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static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
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unsigned int bus, unsigned int dev,
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unsigned int func, unsigned int off)
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{
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u32 addr = 0;
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u32 tmp;
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/* We do only have one cardbus device behind the bridge. */
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if (pc->cardbusmode && (dev >= 1))
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goto out;
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if (bus == 0) {
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/* Type 0 transaction */
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if (unlikely(dev >= SSB_PCI_SLOT_MAX))
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goto out;
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/* Slide the window */
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tmp = SSB_PCICORE_SBTOPCI_CFG0;
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tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
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/* Calculate the address */
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addr = SSB_PCI_CFG;
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addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
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addr |= (func << 8);
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addr |= (off & ~3);
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} else {
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/* Type 1 transaction */
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
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SSB_PCICORE_SBTOPCI_CFG1);
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/* Calculate the address */
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addr = SSB_PCI_CFG;
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addr |= (bus << 16);
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addr |= (dev << 11);
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addr |= (func << 8);
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addr |= (off & ~3);
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}
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out:
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return addr;
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}
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static int ssb_extpci_read_config(struct ssb_pcicore *pc,
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unsigned int bus, unsigned int dev,
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unsigned int func, unsigned int off,
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void *buf, int len)
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{
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int err = -EINVAL;
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u32 addr, val;
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void __iomem *mmio;
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SSB_WARN_ON(!pc->hostmode);
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if (unlikely(len != 1 && len != 2 && len != 4))
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goto out;
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addr = get_cfgspace_addr(pc, bus, dev, func, off);
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if (unlikely(!addr))
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goto out;
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err = -ENOMEM;
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mmio = ioremap_nocache(addr, len);
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if (!mmio)
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goto out;
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if (mips_busprobe32(val, mmio)) {
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val = 0xffffffff;
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goto unmap;
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}
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val = readl(mmio);
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val >>= (8 * (off & 3));
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switch (len) {
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case 1:
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*((u8 *)buf) = (u8)val;
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break;
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case 2:
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*((u16 *)buf) = (u16)val;
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break;
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case 4:
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*((u32 *)buf) = (u32)val;
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break;
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}
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err = 0;
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unmap:
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iounmap(mmio);
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out:
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return err;
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}
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static int ssb_extpci_write_config(struct ssb_pcicore *pc,
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unsigned int bus, unsigned int dev,
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unsigned int func, unsigned int off,
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const void *buf, int len)
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{
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int err = -EINVAL;
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u32 addr, val = 0;
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void __iomem *mmio;
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SSB_WARN_ON(!pc->hostmode);
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if (unlikely(len != 1 && len != 2 && len != 4))
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goto out;
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addr = get_cfgspace_addr(pc, bus, dev, func, off);
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if (unlikely(!addr))
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goto out;
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err = -ENOMEM;
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mmio = ioremap_nocache(addr, len);
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if (!mmio)
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goto out;
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if (mips_busprobe32(val, mmio)) {
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val = 0xffffffff;
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goto unmap;
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}
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switch (len) {
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case 1:
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val = readl(mmio);
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val &= ~(0xFF << (8 * (off & 3)));
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val |= *((const u8 *)buf) << (8 * (off & 3));
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break;
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case 2:
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val = readl(mmio);
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val &= ~(0xFFFF << (8 * (off & 3)));
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val |= *((const u16 *)buf) << (8 * (off & 3));
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break;
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case 4:
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val = *((const u32 *)buf);
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break;
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}
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writel(val, mmio);
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err = 0;
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unmap:
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iounmap(mmio);
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out:
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return err;
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}
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static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
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int reg, int size, u32 *val)
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{
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unsigned long flags;
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int err;
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spin_lock_irqsave(&cfgspace_lock, flags);
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err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), reg, val, size);
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spin_unlock_irqrestore(&cfgspace_lock, flags);
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return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
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int reg, int size, u32 val)
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{
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unsigned long flags;
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int err;
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spin_lock_irqsave(&cfgspace_lock, flags);
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err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), reg, &val, size);
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spin_unlock_irqrestore(&cfgspace_lock, flags);
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return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops ssb_pcicore_pciops = {
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.read = ssb_pcicore_read_config,
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.write = ssb_pcicore_write_config,
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};
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static struct resource ssb_pcicore_mem_resource = {
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.name = "SSB PCIcore external memory",
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.start = SSB_PCI_DMA,
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.end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
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};
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static struct resource ssb_pcicore_io_resource = {
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.name = "SSB PCIcore external I/O",
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.start = 0x100,
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.end = 0x7FF,
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.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
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};
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static struct pci_controller ssb_pcicore_controller = {
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.pci_ops = &ssb_pcicore_pciops,
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.io_resource = &ssb_pcicore_io_resource,
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.mem_resource = &ssb_pcicore_mem_resource,
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};
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/* This function is called when doing a pci_enable_device().
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* We must first check if the device is a device on the PCI-core bridge. */
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int ssb_pcicore_plat_dev_init(struct pci_dev *d)
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{
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if (d->bus->ops != &ssb_pcicore_pciops) {
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/* This is not a device on the PCI-core bridge. */
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return -ENODEV;
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}
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ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
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pci_name(d));
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/* Fix up interrupt lines */
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d->irq = ssb_mips_irq(extpci_core->dev) + 2;
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pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
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return 0;
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}
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/* Early PCI fixup for a device on the PCI-core bridge. */
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static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
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{
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u8 lat;
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if (dev->bus->ops != &ssb_pcicore_pciops) {
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/* This is not a device on the PCI-core bridge. */
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return;
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}
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if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
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return;
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ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
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/* Enable PCI bridge bus mastering and memory space */
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pci_set_master(dev);
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if (pcibios_enable_device(dev, ~0) < 0) {
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ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
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return;
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}
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/* Enable PCI bridge BAR1 prefetch and burst */
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pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
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/* Make sure our latency is high enough to handle the devices behind us */
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lat = 168;
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ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
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pci_name(dev), lat);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
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/* PCI device IRQ mapping. */
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int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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if (dev->bus->ops != &ssb_pcicore_pciops) {
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/* This is not a device on the PCI-core bridge. */
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return -ENODEV;
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}
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return ssb_mips_irq(extpci_core->dev) + 2;
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}
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static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
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{
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u32 val;
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if (WARN_ON(extpci_core))
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return;
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extpci_core = pc;
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ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
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/* Reset devices on the external PCI bus */
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val = SSB_PCICORE_CTL_RST_OE;
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val |= SSB_PCICORE_CTL_CLK_OE;
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pcicore_write32(pc, SSB_PCICORE_CTL, val);
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val |= SSB_PCICORE_CTL_CLK; /* Clock on */
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pcicore_write32(pc, SSB_PCICORE_CTL, val);
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udelay(150); /* Assertion time demanded by the PCI standard */
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val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
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pcicore_write32(pc, SSB_PCICORE_CTL, val);
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val = SSB_PCICORE_ARBCTL_INTERN;
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pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
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udelay(1); /* Assertion time demanded by the PCI standard */
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if (pc->dev->bus->has_cardbus_slot) {
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ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
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pc->cardbusmode = 1;
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/* GPIO 1 resets the bridge */
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ssb_gpio_out(pc->dev->bus, 1, 1);
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ssb_gpio_outen(pc->dev->bus, 1, 1);
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pcicore_write16(pc, SSB_PCICORE_SPROM(0),
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pcicore_read16(pc, SSB_PCICORE_SPROM(0))
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| 0x0400);
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}
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/* 64MB I/O window */
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
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SSB_PCICORE_SBTOPCI_IO);
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/* 64MB config space */
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
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SSB_PCICORE_SBTOPCI_CFG0);
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/* 1GB memory window */
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
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SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
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/* Enable PCI bridge BAR0 prefetch and burst */
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val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
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/* Clear error conditions */
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val = 0;
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ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
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/* Enable PCI interrupts */
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pcicore_write32(pc, SSB_PCICORE_IMASK,
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SSB_PCICORE_IMASK_INTA);
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/* Ok, ready to run, register it to the system.
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* The following needs change, if we want to port hostmode
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* to non-MIPS platform. */
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ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
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set_io_port_base(ssb_pcicore_controller.io_map_base);
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/* Give some time to the PCI controller to configure itself with the new
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* values. Not waiting at this point causes crashes of the machine. */
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mdelay(10);
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register_pci_controller(&ssb_pcicore_controller);
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}
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static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
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{
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struct ssb_bus *bus = pc->dev->bus;
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u16 chipid_top;
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u32 tmp;
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chipid_top = (bus->chip_id & 0xFF00);
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if (chipid_top != 0x4700 &&
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chipid_top != 0x5300)
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return 0;
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if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
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return 0;
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/* The 200-pin BCM4712 package does not bond out PCI. Even when
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* PCI is bonded out, some boards may leave the pins floating. */
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if (bus->chip_id == 0x4712) {
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if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
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return 0;
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if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
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return 0;
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}
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if (bus->chip_id == 0x5350)
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return 0;
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return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
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}
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#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
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/**************************************************
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* Workarounds.
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**************************************************/
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static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
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{
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u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
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if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
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tmp &= ~0xF000;
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tmp |= (pc->dev->core_index << 12);
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pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
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}
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}
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static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
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{
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return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
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}
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static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
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{
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const u8 serdes_pll_device = 0x1D;
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const u8 serdes_rx_device = 0x1F;
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u16 tmp;
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ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
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ssb_pcicore_polarity_workaround(pc));
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tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
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if (tmp & 0x4000)
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ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
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}
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static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
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{
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struct ssb_device *pdev = pc->dev;
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struct ssb_bus *bus = pdev->bus;
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u32 tmp;
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tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
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tmp |= SSB_PCICORE_SBTOPCI_PREF;
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tmp |= SSB_PCICORE_SBTOPCI_BURST;
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pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
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if (pdev->id.revision < 5) {
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tmp = ssb_read32(pdev, SSB_IMCFGLO);
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tmp &= ~SSB_IMCFGLO_SERTO;
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tmp |= 2;
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tmp &= ~SSB_IMCFGLO_REQTO;
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tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
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ssb_write32(pdev, SSB_IMCFGLO, tmp);
|
|
ssb_commit_settings(bus);
|
|
} else if (pdev->id.revision >= 11) {
|
|
tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
|
|
tmp |= SSB_PCICORE_SBTOPCI_MRM;
|
|
pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
|
|
}
|
|
}
|
|
|
|
static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
|
|
{
|
|
u32 tmp;
|
|
u8 rev = pc->dev->id.revision;
|
|
|
|
if (rev == 0 || rev == 1) {
|
|
/* TLP Workaround register. */
|
|
tmp = ssb_pcie_read(pc, 0x4);
|
|
tmp |= 0x8;
|
|
ssb_pcie_write(pc, 0x4, tmp);
|
|
}
|
|
if (rev == 1) {
|
|
/* DLLP Link Control register. */
|
|
tmp = ssb_pcie_read(pc, 0x100);
|
|
tmp |= 0x40;
|
|
ssb_pcie_write(pc, 0x100, tmp);
|
|
}
|
|
|
|
if (rev == 0) {
|
|
const u8 serdes_rx_device = 0x1F;
|
|
|
|
ssb_pcie_mdio_write(pc, serdes_rx_device,
|
|
2 /* Timer */, 0x8128);
|
|
ssb_pcie_mdio_write(pc, serdes_rx_device,
|
|
6 /* CDR */, 0x0100);
|
|
ssb_pcie_mdio_write(pc, serdes_rx_device,
|
|
7 /* CDR BW */, 0x1466);
|
|
} else if (rev == 3 || rev == 4 || rev == 5) {
|
|
/* TODO: DLLP Power Management Threshold */
|
|
ssb_pcicore_serdes_workaround(pc);
|
|
/* TODO: ASPM */
|
|
} else if (rev == 7) {
|
|
/* TODO: No PLL down */
|
|
}
|
|
|
|
if (rev >= 6) {
|
|
/* Miscellaneous Configuration Fixup */
|
|
tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
|
|
if (!(tmp & 0x8000))
|
|
pcicore_write16(pc, SSB_PCICORE_SPROM(5),
|
|
tmp | 0x8000);
|
|
}
|
|
}
|
|
|
|
/**************************************************
|
|
* Generic and Clientmode operation code.
|
|
**************************************************/
|
|
|
|
static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
|
|
{
|
|
ssb_pcicore_fix_sprom_core_index(pc);
|
|
|
|
/* Disable PCI interrupts. */
|
|
ssb_write32(pc->dev, SSB_INTVEC, 0);
|
|
|
|
/* Additional PCIe always once-executed workarounds */
|
|
if (pc->dev->id.coreid == SSB_DEV_PCIE) {
|
|
ssb_pcicore_serdes_workaround(pc);
|
|
/* TODO: ASPM */
|
|
/* TODO: Clock Request Update */
|
|
}
|
|
}
|
|
|
|
void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
|
|
{
|
|
struct ssb_device *dev = pc->dev;
|
|
|
|
if (!dev)
|
|
return;
|
|
if (!ssb_device_is_enabled(dev))
|
|
ssb_device_enable(dev, 0);
|
|
|
|
#ifdef CONFIG_SSB_PCICORE_HOSTMODE
|
|
pc->hostmode = pcicore_is_in_hostmode(pc);
|
|
if (pc->hostmode)
|
|
ssb_pcicore_init_hostmode(pc);
|
|
#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
|
|
if (!pc->hostmode)
|
|
ssb_pcicore_init_clientmode(pc);
|
|
}
|
|
|
|
static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
|
|
{
|
|
pcicore_write32(pc, 0x130, address);
|
|
return pcicore_read32(pc, 0x134);
|
|
}
|
|
|
|
static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
|
|
{
|
|
pcicore_write32(pc, 0x130, address);
|
|
pcicore_write32(pc, 0x134, data);
|
|
}
|
|
|
|
static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
|
|
{
|
|
const u16 mdio_control = 0x128;
|
|
const u16 mdio_data = 0x12C;
|
|
u32 v;
|
|
int i;
|
|
|
|
v = (1 << 30); /* Start of Transaction */
|
|
v |= (1 << 28); /* Write Transaction */
|
|
v |= (1 << 17); /* Turnaround */
|
|
v |= (0x1F << 18);
|
|
v |= (phy << 4);
|
|
pcicore_write32(pc, mdio_data, v);
|
|
|
|
udelay(10);
|
|
for (i = 0; i < 200; i++) {
|
|
v = pcicore_read32(pc, mdio_control);
|
|
if (v & 0x100 /* Trans complete */)
|
|
break;
|
|
msleep(1);
|
|
}
|
|
}
|
|
|
|
static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
|
|
{
|
|
const u16 mdio_control = 0x128;
|
|
const u16 mdio_data = 0x12C;
|
|
int max_retries = 10;
|
|
u16 ret = 0;
|
|
u32 v;
|
|
int i;
|
|
|
|
v = 0x80; /* Enable Preamble Sequence */
|
|
v |= 0x2; /* MDIO Clock Divisor */
|
|
pcicore_write32(pc, mdio_control, v);
|
|
|
|
if (pc->dev->id.revision >= 10) {
|
|
max_retries = 200;
|
|
ssb_pcie_mdio_set_phy(pc, device);
|
|
}
|
|
|
|
v = (1 << 30); /* Start of Transaction */
|
|
v |= (1 << 29); /* Read Transaction */
|
|
v |= (1 << 17); /* Turnaround */
|
|
if (pc->dev->id.revision < 10)
|
|
v |= (u32)device << 22;
|
|
v |= (u32)address << 18;
|
|
pcicore_write32(pc, mdio_data, v);
|
|
/* Wait for the device to complete the transaction */
|
|
udelay(10);
|
|
for (i = 0; i < max_retries; i++) {
|
|
v = pcicore_read32(pc, mdio_control);
|
|
if (v & 0x100 /* Trans complete */) {
|
|
udelay(10);
|
|
ret = pcicore_read32(pc, mdio_data);
|
|
break;
|
|
}
|
|
msleep(1);
|
|
}
|
|
pcicore_write32(pc, mdio_control, 0);
|
|
return ret;
|
|
}
|
|
|
|
static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
|
|
u8 address, u16 data)
|
|
{
|
|
const u16 mdio_control = 0x128;
|
|
const u16 mdio_data = 0x12C;
|
|
int max_retries = 10;
|
|
u32 v;
|
|
int i;
|
|
|
|
v = 0x80; /* Enable Preamble Sequence */
|
|
v |= 0x2; /* MDIO Clock Divisor */
|
|
pcicore_write32(pc, mdio_control, v);
|
|
|
|
if (pc->dev->id.revision >= 10) {
|
|
max_retries = 200;
|
|
ssb_pcie_mdio_set_phy(pc, device);
|
|
}
|
|
|
|
v = (1 << 30); /* Start of Transaction */
|
|
v |= (1 << 28); /* Write Transaction */
|
|
v |= (1 << 17); /* Turnaround */
|
|
if (pc->dev->id.revision < 10)
|
|
v |= (u32)device << 22;
|
|
v |= (u32)address << 18;
|
|
v |= data;
|
|
pcicore_write32(pc, mdio_data, v);
|
|
/* Wait for the device to complete the transaction */
|
|
udelay(10);
|
|
for (i = 0; i < max_retries; i++) {
|
|
v = pcicore_read32(pc, mdio_control);
|
|
if (v & 0x100 /* Trans complete */)
|
|
break;
|
|
msleep(1);
|
|
}
|
|
pcicore_write32(pc, mdio_control, 0);
|
|
}
|
|
|
|
int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
|
|
struct ssb_device *dev)
|
|
{
|
|
struct ssb_device *pdev = pc->dev;
|
|
struct ssb_bus *bus;
|
|
int err = 0;
|
|
u32 tmp;
|
|
|
|
if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
|
|
/* This SSB device is not on a PCI host-bus. So the IRQs are
|
|
* not routed through the PCI core.
|
|
* So we must not enable routing through the PCI core. */
|
|
goto out;
|
|
}
|
|
|
|
if (!pdev)
|
|
goto out;
|
|
bus = pdev->bus;
|
|
|
|
might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
|
|
|
|
/* Enable interrupts for this device. */
|
|
if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
|
|
u32 coremask;
|
|
|
|
/* Calculate the "coremask" for the device. */
|
|
coremask = (1 << dev->core_index);
|
|
|
|
SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
|
|
err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
|
|
if (err)
|
|
goto out;
|
|
tmp |= coremask << 8;
|
|
err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
|
|
if (err)
|
|
goto out;
|
|
} else {
|
|
u32 intvec;
|
|
|
|
intvec = ssb_read32(pdev, SSB_INTVEC);
|
|
tmp = ssb_read32(dev, SSB_TPSFLAG);
|
|
tmp &= SSB_TPSFLAG_BPFLAG;
|
|
intvec |= (1 << tmp);
|
|
ssb_write32(pdev, SSB_INTVEC, intvec);
|
|
}
|
|
|
|
/* Setup PCIcore operation. */
|
|
if (pc->setup_done)
|
|
goto out;
|
|
if (pdev->id.coreid == SSB_DEV_PCI) {
|
|
ssb_pcicore_pci_setup_workarounds(pc);
|
|
} else {
|
|
WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
|
|
ssb_pcicore_pcie_setup_workarounds(pc);
|
|
}
|
|
pc->setup_done = 1;
|
|
out:
|
|
return err;
|
|
}
|
|
EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
|