2f0798a3b1
Combine the timex.h variants and move the TSC related code into tsc.h. Move the set_cyc2ns_scale() call into the tsc calibraction code, where it belongs. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
80 lines
1.8 KiB
C
80 lines
1.8 KiB
C
/*
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* x86 TSC related functions
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*/
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#ifndef _ASM_X86_TSC_H
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#define _ASM_X86_TSC_H
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#include <asm/processor.h>
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#define NS_SCALE 10 /* 2^10, carefully chosen */
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#define US_SCALE 32 /* 2^32, arbitralrily chosen */
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/*
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* Standard way to access the cycle counter.
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*/
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typedef unsigned long long cycles_t;
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extern unsigned int cpu_khz;
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extern unsigned int tsc_khz;
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static inline cycles_t get_cycles(void)
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{
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unsigned long long ret = 0;
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#ifndef CONFIG_X86_TSC
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if (!cpu_has_tsc)
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return 0;
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#endif
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#if defined(CONFIG_X86_GENERIC) || defined(CONFIG_X86_TSC)
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rdtscll(ret);
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#endif
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return ret;
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}
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/* Like get_cycles, but make sure the CPU is synchronized. */
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static __always_inline cycles_t get_cycles_sync(void)
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{
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unsigned long long ret;
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unsigned eax, edx;
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/*
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* Use RDTSCP if possible; it is guaranteed to be synchronous
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* and doesn't cause a VMEXIT on Hypervisors
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*/
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alternative_io(ASM_NOP3, ".byte 0x0f,0x01,0xf9", X86_FEATURE_RDTSCP,
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ASM_OUTPUT2("=a" (eax), "=d" (edx)),
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"a" (0U), "d" (0U) : "ecx", "memory");
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ret = (((unsigned long long)edx) << 32) | ((unsigned long long)eax);
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if (ret)
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return ret;
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/*
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* Don't do an additional sync on CPUs where we know
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* RDTSC is already synchronous:
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*/
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alternative_io("cpuid", ASM_NOP2, X86_FEATURE_SYNC_RDTSC,
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"=a" (eax), "0" (1) : "ebx","ecx","edx","memory");
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rdtscll(ret);
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return ret;
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}
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extern void tsc_init(void);
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extern void mark_tsc_unstable(char *reason);
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extern int unsynchronized_tsc(void);
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extern void init_tsc_clocksource(void);
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int check_tsc_unstable(void);
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/*
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* Boot-time check whether the TSCs are synchronized across
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* all CPUs/cores:
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*/
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extern void check_tsc_sync_source(int cpu);
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extern void check_tsc_sync_target(void);
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#ifdef CONFIG_X86_64
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extern void tsc_calibrate(void);
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#endif
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#endif
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