e43b5ec05a
Virtual address need to be fenced to know when we can safely remove it. This patch also properly clear the pagetable. Previously it was serouisly broken. Kernel 3.5/3.4 need a similar patch but adapted for difference in mutex locking. v2: For to update pagetable when unbinding bo (don't bailout if bo_va->valid is true). v3: Add kernel 3.5/3.4 comment. v4: Fix compilation warnings. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
658 lines
18 KiB
C
658 lines
18 KiB
C
/*
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* Copyright 2008 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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*/
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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void r100_cs_dump_packet(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt);
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int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
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{
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struct drm_device *ddev = p->rdev->ddev;
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struct radeon_cs_chunk *chunk;
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unsigned i, j;
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bool duplicate;
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if (p->chunk_relocs_idx == -1) {
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return 0;
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}
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chunk = &p->chunks[p->chunk_relocs_idx];
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/* FIXME: we assume that each relocs use 4 dwords */
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p->nrelocs = chunk->length_dw / 4;
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p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
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if (p->relocs_ptr == NULL) {
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return -ENOMEM;
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}
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p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
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if (p->relocs == NULL) {
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return -ENOMEM;
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}
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for (i = 0; i < p->nrelocs; i++) {
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struct drm_radeon_cs_reloc *r;
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duplicate = false;
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r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
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for (j = 0; j < i; j++) {
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if (r->handle == p->relocs[j].handle) {
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p->relocs_ptr[i] = &p->relocs[j];
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duplicate = true;
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break;
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}
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}
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if (!duplicate) {
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p->relocs[i].gobj = drm_gem_object_lookup(ddev,
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p->filp,
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r->handle);
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if (p->relocs[i].gobj == NULL) {
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DRM_ERROR("gem object lookup failed 0x%x\n",
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r->handle);
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return -ENOENT;
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}
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p->relocs_ptr[i] = &p->relocs[i];
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p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
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p->relocs[i].lobj.bo = p->relocs[i].robj;
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p->relocs[i].lobj.wdomain = r->write_domain;
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p->relocs[i].lobj.rdomain = r->read_domains;
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p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
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p->relocs[i].handle = r->handle;
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p->relocs[i].flags = r->flags;
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radeon_bo_list_add_object(&p->relocs[i].lobj,
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&p->validated);
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} else
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p->relocs[i].handle = 0;
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}
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return radeon_bo_list_validate(&p->validated);
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}
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static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
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{
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p->priority = priority;
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switch (ring) {
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default:
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DRM_ERROR("unknown ring id: %d\n", ring);
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return -EINVAL;
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case RADEON_CS_RING_GFX:
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p->ring = RADEON_RING_TYPE_GFX_INDEX;
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break;
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case RADEON_CS_RING_COMPUTE:
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if (p->rdev->family >= CHIP_TAHITI) {
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if (p->priority > 0)
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p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
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else
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p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
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} else
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p->ring = RADEON_RING_TYPE_GFX_INDEX;
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break;
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}
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return 0;
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}
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static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
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{
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int i;
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for (i = 0; i < p->nrelocs; i++) {
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struct radeon_fence *a, *b;
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if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
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continue;
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a = p->relocs[i].robj->tbo.sync_obj;
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b = p->ib.sync_to[a->ring];
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p->ib.sync_to[a->ring] = radeon_fence_later(a, b);
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}
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}
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/* XXX: note that this is called from the legacy UMS CS ioctl as well */
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int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
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{
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struct drm_radeon_cs *cs = data;
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uint64_t *chunk_array_ptr;
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unsigned size, i;
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u32 ring = RADEON_CS_RING_GFX;
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s32 priority = 0;
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if (!cs->num_chunks) {
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return 0;
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}
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/* get chunks */
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INIT_LIST_HEAD(&p->validated);
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p->idx = 0;
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p->ib.sa_bo = NULL;
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p->ib.semaphore = NULL;
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p->const_ib.sa_bo = NULL;
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p->const_ib.semaphore = NULL;
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p->chunk_ib_idx = -1;
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p->chunk_relocs_idx = -1;
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p->chunk_flags_idx = -1;
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p->chunk_const_ib_idx = -1;
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p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
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if (p->chunks_array == NULL) {
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return -ENOMEM;
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}
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chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
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if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
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sizeof(uint64_t)*cs->num_chunks)) {
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return -EFAULT;
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}
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p->cs_flags = 0;
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p->nchunks = cs->num_chunks;
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p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
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if (p->chunks == NULL) {
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return -ENOMEM;
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}
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for (i = 0; i < p->nchunks; i++) {
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struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
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struct drm_radeon_cs_chunk user_chunk;
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uint32_t __user *cdata;
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chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
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if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
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sizeof(struct drm_radeon_cs_chunk))) {
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return -EFAULT;
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}
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p->chunks[i].length_dw = user_chunk.length_dw;
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p->chunks[i].kdata = NULL;
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p->chunks[i].chunk_id = user_chunk.chunk_id;
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if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
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p->chunk_relocs_idx = i;
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}
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if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
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p->chunk_ib_idx = i;
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/* zero length IB isn't useful */
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if (p->chunks[i].length_dw == 0)
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return -EINVAL;
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}
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if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
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p->chunk_const_ib_idx = i;
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/* zero length CONST IB isn't useful */
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if (p->chunks[i].length_dw == 0)
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return -EINVAL;
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}
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if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
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p->chunk_flags_idx = i;
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/* zero length flags aren't useful */
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if (p->chunks[i].length_dw == 0)
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return -EINVAL;
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}
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p->chunks[i].length_dw = user_chunk.length_dw;
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p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
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cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
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if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
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(p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
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size = p->chunks[i].length_dw * sizeof(uint32_t);
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p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
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if (p->chunks[i].kdata == NULL) {
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return -ENOMEM;
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}
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if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
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p->chunks[i].user_ptr, size)) {
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return -EFAULT;
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}
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if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
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p->cs_flags = p->chunks[i].kdata[0];
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if (p->chunks[i].length_dw > 1)
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ring = p->chunks[i].kdata[1];
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if (p->chunks[i].length_dw > 2)
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priority = (s32)p->chunks[i].kdata[2];
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}
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}
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}
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/* these are KMS only */
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if (p->rdev) {
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if ((p->cs_flags & RADEON_CS_USE_VM) &&
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!p->rdev->vm_manager.enabled) {
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DRM_ERROR("VM not active on asic!\n");
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return -EINVAL;
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}
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/* we only support VM on SI+ */
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if ((p->rdev->family >= CHIP_TAHITI) &&
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((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
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DRM_ERROR("VM required on SI+!\n");
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return -EINVAL;
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}
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if (radeon_cs_get_ring(p, ring, priority))
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return -EINVAL;
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}
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/* deal with non-vm */
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if ((p->chunk_ib_idx != -1) &&
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((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
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(p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
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if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
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DRM_ERROR("cs IB too big: %d\n",
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p->chunks[p->chunk_ib_idx].length_dw);
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return -EINVAL;
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}
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if ((p->rdev->flags & RADEON_IS_AGP)) {
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p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
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p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
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if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
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p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
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kfree(p->chunks[i].kpage[0]);
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kfree(p->chunks[i].kpage[1]);
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return -ENOMEM;
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}
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}
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p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
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p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
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p->chunks[p->chunk_ib_idx].last_copied_page = -1;
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p->chunks[p->chunk_ib_idx].last_page_index =
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((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
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}
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return 0;
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}
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static void radeon_bo_vm_fence_va(struct radeon_cs_parser *parser,
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struct radeon_fence *fence)
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{
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struct radeon_fpriv *fpriv = parser->filp->driver_priv;
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struct radeon_vm *vm = &fpriv->vm;
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struct radeon_bo_list *lobj;
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if (parser->chunk_ib_idx == -1) {
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return;
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}
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if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) {
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return;
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}
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list_for_each_entry(lobj, &parser->validated, tv.head) {
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struct radeon_bo_va *bo_va;
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struct radeon_bo *rbo = lobj->bo;
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bo_va = radeon_bo_va(rbo, vm);
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radeon_fence_unref(&bo_va->fence);
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bo_va->fence = radeon_fence_ref(fence);
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}
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}
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/**
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* cs_parser_fini() - clean parser states
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* @parser: parser structure holding parsing context.
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* @error: error number
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*
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* If error is set than unvalidate buffer, otherwise just free memory
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* used by parsing context.
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**/
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static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
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{
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unsigned i;
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if (!error) {
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/* fence all bo va before ttm_eu_fence_buffer_objects so bo are still reserved */
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radeon_bo_vm_fence_va(parser, parser->ib.fence);
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ttm_eu_fence_buffer_objects(&parser->validated,
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parser->ib.fence);
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} else {
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ttm_eu_backoff_reservation(&parser->validated);
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}
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if (parser->relocs != NULL) {
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for (i = 0; i < parser->nrelocs; i++) {
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if (parser->relocs[i].gobj)
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drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
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}
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}
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kfree(parser->track);
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kfree(parser->relocs);
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kfree(parser->relocs_ptr);
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for (i = 0; i < parser->nchunks; i++) {
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kfree(parser->chunks[i].kdata);
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if ((parser->rdev->flags & RADEON_IS_AGP)) {
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kfree(parser->chunks[i].kpage[0]);
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kfree(parser->chunks[i].kpage[1]);
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}
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}
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kfree(parser->chunks);
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kfree(parser->chunks_array);
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radeon_ib_free(parser->rdev, &parser->ib);
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radeon_ib_free(parser->rdev, &parser->const_ib);
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}
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static int radeon_cs_ib_chunk(struct radeon_device *rdev,
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struct radeon_cs_parser *parser)
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{
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struct radeon_cs_chunk *ib_chunk;
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int r;
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if (parser->chunk_ib_idx == -1)
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return 0;
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if (parser->cs_flags & RADEON_CS_USE_VM)
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return 0;
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ib_chunk = &parser->chunks[parser->chunk_ib_idx];
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/* Copy the packet into the IB, the parser will read from the
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* input memory (cached) and write to the IB (which can be
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* uncached).
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*/
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r = radeon_ib_get(rdev, parser->ring, &parser->ib,
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ib_chunk->length_dw * 4);
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if (r) {
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DRM_ERROR("Failed to get ib !\n");
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return r;
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}
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parser->ib.length_dw = ib_chunk->length_dw;
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r = radeon_cs_parse(rdev, parser->ring, parser);
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if (r || parser->parser_error) {
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DRM_ERROR("Invalid command stream !\n");
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return r;
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}
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r = radeon_cs_finish_pages(parser);
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if (r) {
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DRM_ERROR("Invalid command stream !\n");
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return r;
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}
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radeon_cs_sync_rings(parser);
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parser->ib.vm_id = 0;
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r = radeon_ib_schedule(rdev, &parser->ib, NULL);
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if (r) {
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DRM_ERROR("Failed to schedule IB !\n");
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}
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return r;
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}
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static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
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struct radeon_vm *vm)
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{
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struct radeon_bo_list *lobj;
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struct radeon_bo *bo;
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int r;
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list_for_each_entry(lobj, &parser->validated, tv.head) {
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bo = lobj->bo;
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r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
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if (r) {
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return r;
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}
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}
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return 0;
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}
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static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
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struct radeon_cs_parser *parser)
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{
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struct radeon_cs_chunk *ib_chunk;
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struct radeon_fpriv *fpriv = parser->filp->driver_priv;
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struct radeon_vm *vm = &fpriv->vm;
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int r;
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if (parser->chunk_ib_idx == -1)
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return 0;
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if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
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return 0;
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if ((rdev->family >= CHIP_TAHITI) &&
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(parser->chunk_const_ib_idx != -1)) {
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ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
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if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
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DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
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return -EINVAL;
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}
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r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
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ib_chunk->length_dw * 4);
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if (r) {
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DRM_ERROR("Failed to get const ib !\n");
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return r;
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}
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parser->const_ib.is_const_ib = true;
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parser->const_ib.length_dw = ib_chunk->length_dw;
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/* Copy the packet into the IB */
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if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
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ib_chunk->length_dw * 4)) {
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return -EFAULT;
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}
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r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
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if (r) {
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return r;
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}
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}
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|
ib_chunk = &parser->chunks[parser->chunk_ib_idx];
|
|
if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
|
|
DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
|
|
return -EINVAL;
|
|
}
|
|
r = radeon_ib_get(rdev, parser->ring, &parser->ib,
|
|
ib_chunk->length_dw * 4);
|
|
if (r) {
|
|
DRM_ERROR("Failed to get ib !\n");
|
|
return r;
|
|
}
|
|
parser->ib.length_dw = ib_chunk->length_dw;
|
|
/* Copy the packet into the IB */
|
|
if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
|
|
ib_chunk->length_dw * 4)) {
|
|
return -EFAULT;
|
|
}
|
|
r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
|
|
mutex_lock(&rdev->vm_manager.lock);
|
|
mutex_lock(&vm->mutex);
|
|
r = radeon_vm_bind(rdev, vm);
|
|
if (r) {
|
|
goto out;
|
|
}
|
|
r = radeon_bo_vm_update_pte(parser, vm);
|
|
if (r) {
|
|
goto out;
|
|
}
|
|
radeon_cs_sync_rings(parser);
|
|
|
|
parser->ib.vm_id = vm->id;
|
|
/* ib pool is bind at 0 in virtual address space,
|
|
* so gpu_addr is the offset inside the pool bo
|
|
*/
|
|
parser->ib.gpu_addr = parser->ib.sa_bo->soffset;
|
|
|
|
if ((rdev->family >= CHIP_TAHITI) &&
|
|
(parser->chunk_const_ib_idx != -1)) {
|
|
parser->const_ib.vm_id = vm->id;
|
|
/* ib pool is bind at 0 in virtual address space,
|
|
* so gpu_addr is the offset inside the pool bo
|
|
*/
|
|
parser->const_ib.gpu_addr = parser->const_ib.sa_bo->soffset;
|
|
r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
|
|
} else {
|
|
r = radeon_ib_schedule(rdev, &parser->ib, NULL);
|
|
}
|
|
|
|
out:
|
|
if (!r) {
|
|
if (vm->fence) {
|
|
radeon_fence_unref(&vm->fence);
|
|
}
|
|
vm->fence = radeon_fence_ref(parser->ib.fence);
|
|
}
|
|
mutex_unlock(&vm->mutex);
|
|
mutex_unlock(&rdev->vm_manager.lock);
|
|
return r;
|
|
}
|
|
|
|
static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
|
|
{
|
|
if (r == -EDEADLK) {
|
|
r = radeon_gpu_reset(rdev);
|
|
if (!r)
|
|
r = -EAGAIN;
|
|
}
|
|
return r;
|
|
}
|
|
|
|
int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
|
|
{
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_cs_parser parser;
|
|
int r;
|
|
|
|
down_read(&rdev->exclusive_lock);
|
|
if (!rdev->accel_working) {
|
|
up_read(&rdev->exclusive_lock);
|
|
return -EBUSY;
|
|
}
|
|
/* initialize parser */
|
|
memset(&parser, 0, sizeof(struct radeon_cs_parser));
|
|
parser.filp = filp;
|
|
parser.rdev = rdev;
|
|
parser.dev = rdev->dev;
|
|
parser.family = rdev->family;
|
|
r = radeon_cs_parser_init(&parser, data);
|
|
if (r) {
|
|
DRM_ERROR("Failed to initialize parser !\n");
|
|
radeon_cs_parser_fini(&parser, r);
|
|
up_read(&rdev->exclusive_lock);
|
|
r = radeon_cs_handle_lockup(rdev, r);
|
|
return r;
|
|
}
|
|
r = radeon_cs_parser_relocs(&parser);
|
|
if (r) {
|
|
if (r != -ERESTARTSYS)
|
|
DRM_ERROR("Failed to parse relocation %d!\n", r);
|
|
radeon_cs_parser_fini(&parser, r);
|
|
up_read(&rdev->exclusive_lock);
|
|
r = radeon_cs_handle_lockup(rdev, r);
|
|
return r;
|
|
}
|
|
r = radeon_cs_ib_chunk(rdev, &parser);
|
|
if (r) {
|
|
goto out;
|
|
}
|
|
r = radeon_cs_ib_vm_chunk(rdev, &parser);
|
|
if (r) {
|
|
goto out;
|
|
}
|
|
out:
|
|
radeon_cs_parser_fini(&parser, r);
|
|
up_read(&rdev->exclusive_lock);
|
|
r = radeon_cs_handle_lockup(rdev, r);
|
|
return r;
|
|
}
|
|
|
|
int radeon_cs_finish_pages(struct radeon_cs_parser *p)
|
|
{
|
|
struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
|
|
int i;
|
|
int size = PAGE_SIZE;
|
|
|
|
for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
|
|
if (i == ibc->last_page_index) {
|
|
size = (ibc->length_dw * 4) % PAGE_SIZE;
|
|
if (size == 0)
|
|
size = PAGE_SIZE;
|
|
}
|
|
|
|
if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
|
|
ibc->user_ptr + (i * PAGE_SIZE),
|
|
size))
|
|
return -EFAULT;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
|
|
{
|
|
int new_page;
|
|
struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
|
|
int i;
|
|
int size = PAGE_SIZE;
|
|
bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
|
|
|
|
for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
|
|
if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
|
|
ibc->user_ptr + (i * PAGE_SIZE),
|
|
PAGE_SIZE)) {
|
|
p->parser_error = -EFAULT;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
if (pg_idx == ibc->last_page_index) {
|
|
size = (ibc->length_dw * 4) % PAGE_SIZE;
|
|
if (size == 0)
|
|
size = PAGE_SIZE;
|
|
}
|
|
|
|
new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
|
|
if (copy1)
|
|
ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
|
|
|
|
if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
|
|
ibc->user_ptr + (pg_idx * PAGE_SIZE),
|
|
size)) {
|
|
p->parser_error = -EFAULT;
|
|
return 0;
|
|
}
|
|
|
|
/* copy to IB for non single case */
|
|
if (!copy1)
|
|
memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
|
|
|
|
ibc->last_copied_page = pg_idx;
|
|
ibc->kpage_idx[new_page] = pg_idx;
|
|
|
|
return new_page;
|
|
}
|
|
|
|
u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
|
|
{
|
|
struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
|
|
u32 pg_idx, pg_offset;
|
|
u32 idx_value = 0;
|
|
int new_page;
|
|
|
|
pg_idx = (idx * 4) / PAGE_SIZE;
|
|
pg_offset = (idx * 4) % PAGE_SIZE;
|
|
|
|
if (ibc->kpage_idx[0] == pg_idx)
|
|
return ibc->kpage[0][pg_offset/4];
|
|
if (ibc->kpage_idx[1] == pg_idx)
|
|
return ibc->kpage[1][pg_offset/4];
|
|
|
|
new_page = radeon_cs_update_pages(p, pg_idx);
|
|
if (new_page < 0) {
|
|
p->parser_error = new_page;
|
|
return 0;
|
|
}
|
|
|
|
idx_value = ibc->kpage[new_page][pg_offset/4];
|
|
return idx_value;
|
|
}
|