c420b2dc8d
Been tested on each major revision that's relevant here, but I'm sure there are still bugs waiting to be ironed out. This is a *very* invasive change. There's a couple of pieces left that I don't like much (eg. other engines using fifo_priv for the channel count), but that's an artefact of there being a master channel list still. This is changing, slowly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
467 lines
13 KiB
C
467 lines
13 KiB
C
/*
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* Copyright (C) 2007 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_fifo.h"
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#include "nouveau_ramht.h"
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struct nv40_graph_engine {
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struct nouveau_exec_engine base;
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u32 grctx_size;
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};
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static int
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nv40_graph_context_new(struct nouveau_channel *chan, int engine)
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{
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struct nv40_graph_engine *pgraph = nv_engine(chan->dev, engine);
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *grctx = NULL;
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unsigned long flags;
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int ret;
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ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
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NVOBJ_FLAG_ZERO_ALLOC, &grctx);
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if (ret)
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return ret;
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/* Initialise default context values */
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nv40_grctx_fill(dev, grctx);
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nv_wo32(grctx, 0, grctx->vinst);
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/* init grctx pointer in ramfc, and on PFIFO if channel is
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* already active there
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*/
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_wo32(chan->ramfc, 0x38, grctx->vinst >> 4);
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nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
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if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
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nv_wr32(dev, 0x0032e0, grctx->vinst >> 4);
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nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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chan->engctx[engine] = grctx;
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return 0;
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}
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static void
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nv40_graph_context_del(struct nouveau_channel *chan, int engine)
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{
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struct nouveau_gpuobj *grctx = chan->engctx[engine];
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 inst = 0x01000000 | (grctx->pinst >> 4);
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unsigned long flags;
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_mask(dev, 0x400720, 0x00000000, 0x00000001);
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if (nv_rd32(dev, 0x40032c) == inst)
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nv_mask(dev, 0x40032c, 0x01000000, 0x00000000);
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if (nv_rd32(dev, 0x400330) == inst)
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nv_mask(dev, 0x400330, 0x01000000, 0x00000000);
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nv_mask(dev, 0x400720, 0x00000001, 0x00000001);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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/* Free the context resources */
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nouveau_gpuobj_ref(NULL, &grctx);
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chan->engctx[engine] = NULL;
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}
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int
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nv40_graph_object_new(struct nouveau_channel *chan, int engine,
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u32 handle, u16 class)
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{
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struct drm_device *dev = chan->dev;
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struct nouveau_gpuobj *obj = NULL;
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int ret;
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ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
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if (ret)
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return ret;
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obj->engine = 1;
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obj->class = class;
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nv_wo32(obj, 0x00, class);
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nv_wo32(obj, 0x04, 0x00000000);
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#ifndef __BIG_ENDIAN
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nv_wo32(obj, 0x08, 0x00000000);
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#else
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nv_wo32(obj, 0x08, 0x01000000);
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#endif
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nv_wo32(obj, 0x0c, 0x00000000);
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nv_wo32(obj, 0x10, 0x00000000);
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ret = nouveau_ramht_insert(chan, handle, obj);
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nouveau_gpuobj_ref(NULL, &obj);
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return ret;
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}
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static void
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nv40_graph_set_tile_region(struct drm_device *dev, int i)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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switch (dev_priv->chipset) {
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case 0x40:
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case 0x41: /* guess */
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case 0x42:
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case 0x43:
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case 0x45: /* guess */
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case 0x4e:
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nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
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nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
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nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
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nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
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nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
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nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
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break;
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case 0x44:
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case 0x4a:
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nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
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nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
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nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
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break;
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case 0x46:
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case 0x47:
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case 0x49:
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case 0x4b:
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case 0x4c:
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case 0x67:
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default:
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nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
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nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
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nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
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nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
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nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
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nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
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break;
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}
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}
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/*
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* G70 0x47
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* G71 0x49
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* NV45 0x48
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* G72[M] 0x46
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* G73 0x4b
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* C51_G7X 0x4c
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* C51 0x4e
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*/
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int
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nv40_graph_init(struct drm_device *dev, int engine)
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{
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struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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uint32_t vramsz;
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int i, j;
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
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~NV_PMC_ENABLE_PGRAPH);
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
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NV_PMC_ENABLE_PGRAPH);
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/* generate and upload context program */
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nv40_grctx_init(dev, &pgraph->grctx_size);
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/* No context present currently */
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
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nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
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nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
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nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
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nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
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nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
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nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
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nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
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nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
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nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
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nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
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j = nv_rd32(dev, 0x1540) & 0xff;
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if (j) {
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for (i = 0; !(j & 1); j >>= 1, i++)
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;
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nv_wr32(dev, 0x405000, i);
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}
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if (dev_priv->chipset == 0x40) {
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nv_wr32(dev, 0x4009b0, 0x83280fff);
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nv_wr32(dev, 0x4009b4, 0x000000a0);
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} else {
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nv_wr32(dev, 0x400820, 0x83280eff);
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nv_wr32(dev, 0x400824, 0x000000a0);
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}
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switch (dev_priv->chipset) {
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case 0x40:
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case 0x45:
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nv_wr32(dev, 0x4009b8, 0x0078e366);
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nv_wr32(dev, 0x4009bc, 0x0000014c);
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break;
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case 0x41:
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case 0x42: /* pciid also 0x00Cx */
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/* case 0x0120: XXX (pciid) */
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nv_wr32(dev, 0x400828, 0x007596ff);
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nv_wr32(dev, 0x40082c, 0x00000108);
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break;
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case 0x43:
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nv_wr32(dev, 0x400828, 0x0072cb77);
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nv_wr32(dev, 0x40082c, 0x00000108);
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break;
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case 0x44:
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case 0x46: /* G72 */
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case 0x4a:
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case 0x4c: /* G7x-based C51 */
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case 0x4e:
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nv_wr32(dev, 0x400860, 0);
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nv_wr32(dev, 0x400864, 0);
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break;
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case 0x47: /* G70 */
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case 0x49: /* G71 */
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case 0x4b: /* G73 */
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nv_wr32(dev, 0x400828, 0x07830610);
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nv_wr32(dev, 0x40082c, 0x0000016A);
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break;
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default:
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break;
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}
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nv_wr32(dev, 0x400b38, 0x2ffff800);
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nv_wr32(dev, 0x400b3c, 0x00006000);
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/* Tiling related stuff. */
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switch (dev_priv->chipset) {
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case 0x44:
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case 0x4a:
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nv_wr32(dev, 0x400bc4, 0x1003d888);
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nv_wr32(dev, 0x400bbc, 0xb7a7b500);
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break;
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case 0x46:
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nv_wr32(dev, 0x400bc4, 0x0000e024);
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nv_wr32(dev, 0x400bbc, 0xb7a7b520);
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break;
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case 0x4c:
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case 0x4e:
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case 0x67:
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nv_wr32(dev, 0x400bc4, 0x1003d888);
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nv_wr32(dev, 0x400bbc, 0xb7a7b540);
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break;
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default:
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break;
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}
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/* Turn all the tiling regions off. */
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for (i = 0; i < pfb->num_tiles; i++)
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nv40_graph_set_tile_region(dev, i);
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/* begin RAM config */
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vramsz = pci_resource_len(dev->pdev, 0) - 1;
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switch (dev_priv->chipset) {
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case 0x40:
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nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
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nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
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nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
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nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
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nv_wr32(dev, 0x400820, 0);
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nv_wr32(dev, 0x400824, 0);
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nv_wr32(dev, 0x400864, vramsz);
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nv_wr32(dev, 0x400868, vramsz);
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break;
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default:
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switch (dev_priv->chipset) {
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x45:
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case 0x4e:
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case 0x44:
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case 0x4a:
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nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
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nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
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break;
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default:
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nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
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nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
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break;
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}
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nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
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nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
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nv_wr32(dev, 0x400840, 0);
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nv_wr32(dev, 0x400844, 0);
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nv_wr32(dev, 0x4008A0, vramsz);
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nv_wr32(dev, 0x4008A4, vramsz);
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break;
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}
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return 0;
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}
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static int
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nv40_graph_fini(struct drm_device *dev, int engine, bool suspend)
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{
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u32 inst = nv_rd32(dev, 0x40032c);
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if (inst & 0x01000000) {
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nv_wr32(dev, 0x400720, 0x00000000);
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nv_wr32(dev, 0x400784, inst);
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nv_mask(dev, 0x400310, 0x00000020, 0x00000020);
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nv_mask(dev, 0x400304, 0x00000001, 0x00000001);
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if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000)) {
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u32 insn = nv_rd32(dev, 0x400308);
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NV_ERROR(dev, "PGRAPH: ctxprog timeout 0x%08x\n", insn);
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}
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nv_mask(dev, 0x40032c, 0x01000000, 0x00000000);
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}
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return 0;
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}
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static int
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nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
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{
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struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *grctx;
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unsigned long flags;
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int i;
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spin_lock_irqsave(&dev_priv->channels.lock, flags);
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for (i = 0; i < pfifo->channels; i++) {
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if (!dev_priv->channels.ptr[i])
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continue;
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grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
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if (grctx && grctx->pinst == inst)
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break;
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}
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spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
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return i;
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}
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static void
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nv40_graph_isr(struct drm_device *dev)
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{
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u32 stat;
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while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
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u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
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u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
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u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
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u32 chid = nv40_graph_isr_chid(dev, inst);
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u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
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u32 subc = (addr & 0x00070000) >> 16;
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u32 mthd = (addr & 0x00001ffc);
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u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
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u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
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u32 show = stat;
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if (stat & NV_PGRAPH_INTR_ERROR) {
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if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
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if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
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show &= ~NV_PGRAPH_INTR_ERROR;
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} else
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if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
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nv_mask(dev, 0x402000, 0, 0);
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}
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}
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nv_wr32(dev, NV03_PGRAPH_INTR, stat);
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nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
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if (show && nouveau_ratelimit()) {
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NV_INFO(dev, "PGRAPH -");
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nouveau_bitfield_print(nv10_graph_intr, show);
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printk(" nsource:");
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nouveau_bitfield_print(nv04_graph_nsource, nsource);
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printk(" nstatus:");
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nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
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printk("\n");
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NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
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"class 0x%04x mthd 0x%04x data 0x%08x\n",
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chid, inst, subc, class, mthd, data);
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}
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}
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}
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static void
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nv40_graph_destroy(struct drm_device *dev, int engine)
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{
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struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
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nouveau_irq_unregister(dev, 12);
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NVOBJ_ENGINE_DEL(dev, GR);
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kfree(pgraph);
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}
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int
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nv40_graph_create(struct drm_device *dev)
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{
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struct nv40_graph_engine *pgraph;
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pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
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if (!pgraph)
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return -ENOMEM;
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pgraph->base.destroy = nv40_graph_destroy;
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pgraph->base.init = nv40_graph_init;
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pgraph->base.fini = nv40_graph_fini;
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pgraph->base.context_new = nv40_graph_context_new;
|
|
pgraph->base.context_del = nv40_graph_context_del;
|
|
pgraph->base.object_new = nv40_graph_object_new;
|
|
pgraph->base.set_tile_region = nv40_graph_set_tile_region;
|
|
|
|
NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
|
|
nouveau_irq_register(dev, 12, nv40_graph_isr);
|
|
|
|
NVOBJ_CLASS(dev, 0x0030, GR); /* null */
|
|
NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
|
|
NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
|
|
NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
|
|
NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
|
|
NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
|
|
NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
|
|
NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
|
|
NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
|
|
NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
|
|
NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
|
|
NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
|
|
NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
|
|
NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
|
|
NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
|
|
|
|
/* curie */
|
|
if (nv44_graph_class(dev))
|
|
NVOBJ_CLASS(dev, 0x4497, GR);
|
|
else
|
|
NVOBJ_CLASS(dev, 0x4097, GR);
|
|
|
|
return 0;
|
|
}
|