c420b2dc8d
Been tested on each major revision that's relevant here, but I'm sure there are still bugs waiting to be ironed out. This is a *very* invasive change. There's a couple of pieces left that I don't like much (eg. other engines using fifo_priv for the channel count), but that's an artefact of there being a master channel list still. This is changing, slowly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
138 lines
4.3 KiB
C
138 lines
4.3 KiB
C
/*
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* Copyright (C) 2012 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_fifo.h"
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#include "nouveau_util.h"
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#include "nouveau_ramht.h"
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static struct ramfc_desc {
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unsigned bits:6;
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unsigned ctxs:5;
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unsigned ctxp:8;
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unsigned regs:5;
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unsigned regp;
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} nv10_ramfc[] = {
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{ 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
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{ 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
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{ 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
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{ 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
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{ 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
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{ 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE },
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{ 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
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{ 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE },
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{ 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 },
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{}
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};
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struct nv10_fifo_priv {
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struct nouveau_fifo_priv base;
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struct ramfc_desc *ramfc_desc;
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};
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struct nv10_fifo_chan {
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struct nouveau_fifo_chan base;
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struct nouveau_gpuobj *ramfc;
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};
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static int
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nv10_fifo_context_new(struct nouveau_channel *chan, int engine)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv10_fifo_priv *priv = nv_engine(dev, engine);
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struct nv10_fifo_chan *fctx;
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unsigned long flags;
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int ret;
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fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
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if (!fctx)
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return -ENOMEM;
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/* map channel control registers */
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chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
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NV03_USER(chan->id), PAGE_SIZE);
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if (!chan->user) {
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ret = -ENOMEM;
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goto error;
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}
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/* initialise default fifo context */
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ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramfc->pinst +
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chan->id * 32, ~0, 32,
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NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc);
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if (ret)
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goto error;
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nv_wo32(fctx->ramfc, 0x00, chan->pushbuf_base);
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nv_wo32(fctx->ramfc, 0x04, chan->pushbuf_base);
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nv_wo32(fctx->ramfc, 0x08, 0x00000000);
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nv_wo32(fctx->ramfc, 0x0c, chan->pushbuf->pinst >> 4);
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nv_wo32(fctx->ramfc, 0x10, 0x00000000);
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nv_wo32(fctx->ramfc, 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
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#ifdef __BIG_ENDIAN
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NV_PFIFO_CACHE1_BIG_ENDIAN |
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#endif
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NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
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nv_wo32(fctx->ramfc, 0x18, 0x00000000);
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nv_wo32(fctx->ramfc, 0x1c, 0x00000000);
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/* enable dma mode on the channel */
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_mask(dev, NV04_PFIFO_MODE, (1 << chan->id), (1 << chan->id));
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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error:
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if (ret)
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priv->base.base.context_del(chan, engine);
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return ret;
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}
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int
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nv10_fifo_create(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv10_fifo_priv *priv;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base.base.destroy = nv04_fifo_destroy;
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priv->base.base.init = nv04_fifo_init;
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priv->base.base.fini = nv04_fifo_fini;
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priv->base.base.context_new = nv10_fifo_context_new;
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priv->base.base.context_del = nv04_fifo_context_del;
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priv->base.channels = 31;
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priv->ramfc_desc = nv10_ramfc;
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dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base;
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nouveau_irq_register(dev, 8, nv04_fifo_isr);
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return 0;
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}
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