fd88edd20f
Add base definitions for the AC97 register definitions. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
253 lines
7.8 KiB
C
253 lines
7.8 KiB
C
/* linux/include/asm-arm/arch-s3c2410/map.h
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*
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* (c) 2003 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H
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/* we have a bit of a tight squeeze to fit all our registers from
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* 0xF00000000 upwards, since we use all of the nGCS space in some
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* capacity, and also need to fit the S3C2410 registers in as well...
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*
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* we try to ensure stuff like the IRQ registers are available for
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* an single MOVS instruction (ie, only 8 bits of set data)
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*
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* Note, we are trying to remove some of these from the implementation
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* as they are only useful to certain drivers...
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*/
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#ifndef __ASSEMBLY__
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#define S3C2410_ADDR(x) ((void __iomem *)0xF0000000 + (x))
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#else
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#define S3C2410_ADDR(x) (0xF0000000 + (x))
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#endif
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#define S3C2400_ADDR(x) S3C2410_ADDR(x)
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/* interrupt controller is the first thing we put in, to make
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* the assembly code for the irq detection easier
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*/
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#define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000)
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#define S3C2400_PA_IRQ (0x14400000)
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#define S3C2410_PA_IRQ (0x4A000000)
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#define S3C24XX_SZ_IRQ SZ_1M
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/* memory controller registers */
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#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
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#define S3C2400_PA_MEMCTRL (0x14000000)
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#define S3C2410_PA_MEMCTRL (0x48000000)
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#define S3C24XX_SZ_MEMCTRL SZ_1M
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/* USB host controller */
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#define S3C24XX_VA_USBHOST S3C2410_ADDR(0x00200000)
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#define S3C2400_PA_USBHOST (0x14200000)
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#define S3C2410_PA_USBHOST (0x49000000)
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#define S3C24XX_SZ_USBHOST SZ_1M
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/* DMA controller */
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#define S3C24XX_VA_DMA S3C2410_ADDR(0x00300000)
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#define S3C2400_PA_DMA (0x14600000)
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#define S3C2410_PA_DMA (0x4B000000)
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#define S3C24XX_SZ_DMA SZ_1M
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/* Clock and Power management */
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#define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00400000)
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#define S3C2400_PA_CLKPWR (0x14800000)
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#define S3C2410_PA_CLKPWR (0x4C000000)
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#define S3C24XX_SZ_CLKPWR SZ_1M
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/* LCD controller */
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#define S3C24XX_VA_LCD S3C2410_ADDR(0x00600000)
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#define S3C2400_PA_LCD (0x14A00000)
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#define S3C2410_PA_LCD (0x4D000000)
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#define S3C24XX_SZ_LCD SZ_1M
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/* NAND flash controller */
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#define S3C24XX_VA_NAND S3C2410_ADDR(0x00700000)
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#define S3C2410_PA_NAND (0x4E000000)
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#define S3C24XX_SZ_NAND SZ_1M
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/* MMC controller - available on the S3C2400 */
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#define S3C2400_VA_MMC S3C2400_ADDR(0x00700000)
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#define S3C2400_PA_MMC (0x15A00000)
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#define S3C2400_SZ_MMC SZ_1M
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/* UARTs */
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#define S3C24XX_VA_UART S3C2410_ADDR(0x00800000)
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#define S3C2400_PA_UART (0x15000000)
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#define S3C2410_PA_UART (0x50000000)
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#define S3C24XX_SZ_UART SZ_1M
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/* Timers */
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#define S3C24XX_VA_TIMER S3C2410_ADDR(0x00900000)
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#define S3C2400_PA_TIMER (0x15100000)
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#define S3C2410_PA_TIMER (0x51000000)
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#define S3C24XX_SZ_TIMER SZ_1M
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/* USB Device port */
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#define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00A00000)
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#define S3C2400_PA_USBDEV (0x15200140)
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#define S3C2410_PA_USBDEV (0x52000000)
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#define S3C24XX_SZ_USBDEV SZ_1M
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/* Watchdog */
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#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00B00000)
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#define S3C2400_PA_WATCHDOG (0x15300000)
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#define S3C2410_PA_WATCHDOG (0x53000000)
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#define S3C24XX_SZ_WATCHDOG SZ_1M
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/* IIC hardware controller */
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#define S3C24XX_VA_IIC S3C2410_ADDR(0x00C00000)
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#define S3C2400_PA_IIC (0x15400000)
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#define S3C2410_PA_IIC (0x54000000)
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#define S3C24XX_SZ_IIC SZ_1M
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#define VA_IIC_BASE (S3C24XX_VA_IIC)
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/* IIS controller */
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#define S3C24XX_VA_IIS S3C2410_ADDR(0x00D00000)
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#define S3C2400_PA_IIS (0x15508000)
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#define S3C2410_PA_IIS (0x55000000)
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#define S3C24XX_SZ_IIS SZ_1M
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/* GPIO ports */
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/* the calculation for the VA of this must ensure that
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* it is the same distance apart from the UART in the
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* phsyical address space, as the initial mapping for the IO
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* is done as a 1:1 maping. This puts it (currently) at
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* 0xF6800000, which is not in the way of any current mapping
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* by the base system.
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*/
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#define S3C2400_PA_GPIO (0x15600000)
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#define S3C2410_PA_GPIO (0x56000000)
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#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
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#define S3C24XX_SZ_GPIO SZ_1M
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/* RTC */
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#define S3C24XX_VA_RTC S3C2410_ADDR(0x00F00000)
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#define S3C2400_PA_RTC (0x15700040)
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#define S3C2410_PA_RTC (0x57000000)
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#define S3C24XX_SZ_RTC SZ_1M
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/* ADC */
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#define S3C24XX_VA_ADC S3C2410_ADDR(0x01000000)
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#define S3C2400_PA_ADC (0x15800000)
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#define S3C2410_PA_ADC (0x58000000)
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#define S3C24XX_SZ_ADC SZ_1M
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/* SPI */
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#define S3C24XX_VA_SPI S3C2410_ADDR(0x01100000)
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#define S3C2400_PA_SPI (0x15900000)
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#define S3C2410_PA_SPI (0x59000000)
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#define S3C24XX_SZ_SPI SZ_1M
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/* SDI */
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#define S3C24XX_VA_SDI S3C2410_ADDR(0x01200000)
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#define S3C2410_PA_SDI (0x5A000000)
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#define S3C24XX_SZ_SDI SZ_1M
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/* CAMIF */
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#define S3C2440_PA_CAMIF (0x4F000000)
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#define S3C2440_SZ_CAMIF SZ_1M
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/* AC97 */
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#define S3C2440_PA_AC97 (0x5B000000)
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#define S3C2440_SZ_AC97 SZ_1M
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/* ISA style IO, for each machine to sort out mappings for, if it
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* implements it. We reserve two 16M regions for ISA.
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*/
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#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
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#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
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/* physical addresses of all the chip-select areas */
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#define S3C2410_CS0 (0x00000000)
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#define S3C2410_CS1 (0x08000000)
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#define S3C2410_CS2 (0x10000000)
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#define S3C2410_CS3 (0x18000000)
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#define S3C2410_CS4 (0x20000000)
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#define S3C2410_CS5 (0x28000000)
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#define S3C2410_CS6 (0x30000000)
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#define S3C2410_CS7 (0x38000000)
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#define S3C2410_SDRAM_PA (S3C2410_CS6)
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#define S3C2400_CS0 (0x00000000)
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#define S3C2400_CS1 (0x02000000)
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#define S3C2400_CS2 (0x04000000)
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#define S3C2400_CS3 (0x06000000)
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#define S3C2400_CS4 (0x08000000)
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#define S3C2400_CS5 (0x0A000000)
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#define S3C2400_CS6 (0x0C000000)
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#define S3C2400_CS7 (0x0E000000)
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#define S3C2400_SDRAM_PA (S3C2400_CS6)
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/* Use a single interface for common resources between S3C24XX cpus */
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#ifdef CONFIG_CPU_S3C2400
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#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
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#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
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#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
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#define S3C24XX_PA_DMA S3C2400_PA_DMA
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#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
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#define S3C24XX_PA_LCD S3C2400_PA_LCD
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#define S3C24XX_PA_UART S3C2400_PA_UART
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#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
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#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
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#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
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#define S3C24XX_PA_IIC S3C2400_PA_IIC
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#define S3C24XX_PA_IIS S3C2400_PA_IIS
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#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
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#define S3C24XX_PA_RTC S3C2400_PA_RTC
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#define S3C24XX_PA_ADC S3C2400_PA_ADC
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#define S3C24XX_PA_SPI S3C2400_PA_SPI
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#else
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#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
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#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
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#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
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#define S3C24XX_PA_DMA S3C2410_PA_DMA
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#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
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#define S3C24XX_PA_LCD S3C2410_PA_LCD
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#define S3C24XX_PA_UART S3C2410_PA_UART
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#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
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#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
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#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
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#define S3C24XX_PA_IIC S3C2410_PA_IIC
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#define S3C24XX_PA_IIS S3C2410_PA_IIS
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#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
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#define S3C24XX_PA_RTC S3C2410_PA_RTC
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#define S3C24XX_PA_ADC S3C2410_PA_ADC
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#define S3C24XX_PA_SPI S3C2410_PA_SPI
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#endif
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/* deal with the registers that move under the 2412/2413 */
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#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
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#ifndef __ASSEMBLY__
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extern void __iomem *s3c24xx_va_gpio2;
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#endif
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#ifdef CONFIG_CPU_S3C2412_ONLY
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#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
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#else
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#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
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#endif
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#else
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#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
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#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
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#endif
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#endif /* __ASM_ARCH_MAP_H */
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