510 lines
14 KiB
C
510 lines
14 KiB
C
/*
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* Copyright (c) 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicensen
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Thomas Eaton <thomas.g.eaton@intel.com>
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* Scott Rowe <scott.m.rowe@intel.com>
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*/
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#include "mdfld_dsi_dbi.h"
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#include "mdfld_dsi_dpi.h"
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#include "mdfld_dsi_output.h"
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#include "mdfld_output.h"
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#include "mdfld_dsi_dbi_dpu.h"
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#include "mdfld_dsi_pkg_sender.h"
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#include "displays/tpo_cmd.h"
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static struct drm_display_mode *tpo_cmd_get_config_mode(struct drm_device *dev)
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{
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struct drm_display_mode *mode;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct mrst_timing_info *ti = &dev_priv->gct_data.DTD;
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bool use_gct = false;
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mode = kzalloc(sizeof(*mode), GFP_KERNEL);
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if (!mode)
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return NULL;
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if (use_gct) {
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dev_dbg(dev->dev, "gct find MIPI panel.\n");
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mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
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mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
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mode->hsync_start = mode->hdisplay + \
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((ti->hsync_offset_hi << 8) | \
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ti->hsync_offset_lo);
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mode->hsync_end = mode->hsync_start + \
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((ti->hsync_pulse_width_hi << 8) | \
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ti->hsync_pulse_width_lo);
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mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
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ti->hblank_lo);
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mode->vsync_start = \
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mode->vdisplay + ((ti->vsync_offset_hi << 8) | \
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ti->vsync_offset_lo);
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mode->vsync_end = \
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mode->vsync_start + ((ti->vsync_pulse_width_hi << 8) | \
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ti->vsync_pulse_width_lo);
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mode->vtotal = mode->vdisplay + \
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((ti->vblank_hi << 8) | ti->vblank_lo);
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mode->clock = ti->pixel_clock * 10;
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dev_dbg(dev->dev, "hdisplay is %d\n", mode->hdisplay);
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dev_dbg(dev->dev, "vdisplay is %d\n", mode->vdisplay);
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dev_dbg(dev->dev, "HSS is %d\n", mode->hsync_start);
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dev_dbg(dev->dev, "HSE is %d\n", mode->hsync_end);
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dev_dbg(dev->dev, "htotal is %d\n", mode->htotal);
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dev_dbg(dev->dev, "VSS is %d\n", mode->vsync_start);
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dev_dbg(dev->dev, "VSE is %d\n", mode->vsync_end);
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dev_dbg(dev->dev, "vtotal is %d\n", mode->vtotal);
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dev_dbg(dev->dev, "clock is %d\n", mode->clock);
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} else {
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mode->hdisplay = 864;
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mode->vdisplay = 480;
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mode->hsync_start = 872;
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mode->hsync_end = 876;
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mode->htotal = 884;
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mode->vsync_start = 482;
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mode->vsync_end = 494;
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mode->vtotal = 486;
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mode->clock = 25777;
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}
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drm_mode_set_name(mode);
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drm_mode_set_crtcinfo(mode, 0);
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mode->type |= DRM_MODE_TYPE_PREFERRED;
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return mode;
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}
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static bool mdfld_dsi_dbi_mode_fixup(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_display_mode *fixed_mode = tpo_cmd_get_config_mode(dev);
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if (fixed_mode) {
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adjusted_mode->hdisplay = fixed_mode->hdisplay;
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adjusted_mode->hsync_start = fixed_mode->hsync_start;
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adjusted_mode->hsync_end = fixed_mode->hsync_end;
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adjusted_mode->htotal = fixed_mode->htotal;
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adjusted_mode->vdisplay = fixed_mode->vdisplay;
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adjusted_mode->vsync_start = fixed_mode->vsync_start;
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adjusted_mode->vsync_end = fixed_mode->vsync_end;
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adjusted_mode->vtotal = fixed_mode->vtotal;
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adjusted_mode->clock = fixed_mode->clock;
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drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
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kfree(fixed_mode);
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}
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return true;
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}
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static void mdfld_dsi_dbi_set_power(struct drm_encoder *encoder, bool on)
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{
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int ret = 0;
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struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
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struct mdfld_dsi_dbi_output *dbi_output =
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MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
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struct mdfld_dsi_config *dsi_config =
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mdfld_dsi_encoder_get_config(dsi_encoder);
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struct mdfld_dsi_pkg_sender *sender =
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mdfld_dsi_encoder_get_pkg_sender(dsi_encoder);
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struct drm_device *dev = encoder->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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u32 reg_offset = 0;
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int pipe = (dbi_output->channel_num == 0) ? 0 : 2;
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u32 data = 0;
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dev_dbg(dev->dev, "pipe %d : %s, panel on: %s\n",
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pipe, on ? "On" : "Off",
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dbi_output->dbi_panel_on ? "True" : "False");
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if (pipe == 2) {
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if (on)
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dev_priv->dual_mipi = true;
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else
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dev_priv->dual_mipi = false;
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reg_offset = MIPIC_REG_OFFSET;
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} else {
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if (!on)
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dev_priv->dual_mipi = false;
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}
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if (!gma_power_begin(dev, true)) {
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dev_err(dev->dev, "hw begin failed\n");
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return;
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}
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if (on) {
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if (dbi_output->dbi_panel_on)
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goto out_err;
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ret = mdfld_dsi_dbi_update_power(dbi_output, DRM_MODE_DPMS_ON);
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if (ret) {
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dev_err(dev->dev, "power on error\n");
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goto out_err;
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}
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dbi_output->dbi_panel_on = true;
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if (pipe == 2)
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dev_priv->dbi_panel_on2 = true;
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else
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dev_priv->dbi_panel_on = true;
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mdfld_enable_te(dev, pipe);
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} else {
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if (!dbi_output->dbi_panel_on && !dbi_output->first_boot)
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goto out_err;
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dbi_output->dbi_panel_on = false;
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dbi_output->first_boot = false;
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if (pipe == 2)
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dev_priv->dbi_panel_on2 = false;
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else
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dev_priv->dbi_panel_on = false;
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mdfld_disable_te(dev, pipe);
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ret = mdfld_dsi_dbi_update_power(dbi_output, DRM_MODE_DPMS_OFF);
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if (ret) {
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dev_err(dev->dev, "power on error\n");
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goto out_err;
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}
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}
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/*
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* FIXME: this is a WA for TPO panel crash on DPMS on & off around
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* 83 times. the root cause of this issue is that Booster in
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* drvIC crashed. Add this WA so that we can resume the driver IC
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* once we found that booster has a fault
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*/
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mdfld_dsi_get_power_mode(dsi_config,
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&data,
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MDFLD_DSI_HS_TRANSMISSION);
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if (on && data && !(data & (1 << 7))) {
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/* Soft reset */
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mdfld_dsi_send_dcs(sender,
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DCS_SOFT_RESET,
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NULL,
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0,
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CMD_DATA_SRC_PIPE,
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MDFLD_DSI_SEND_PACKAGE);
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/* Init drvIC */
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if (dbi_output->p_funcs->drv_ic_init)
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dbi_output->p_funcs->drv_ic_init(dsi_config,
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pipe);
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}
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out_err:
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gma_power_end(dev);
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if (ret)
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dev_err(dev->dev, "failed\n");
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}
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static void mdfld_dsi_dbi_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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int ret = 0;
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struct drm_device *dev = encoder->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
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struct mdfld_dsi_dbi_output *dsi_output =
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MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
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struct mdfld_dsi_config *dsi_config =
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mdfld_dsi_encoder_get_config(dsi_encoder);
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struct mdfld_dsi_connector *dsi_connector = dsi_config->connector;
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int pipe = dsi_connector->pipe;
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u8 param = 0;
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/* Regs */
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u32 mipi_reg = MIPI;
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u32 dspcntr_reg = DSPACNTR;
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u32 pipeconf_reg = PIPEACONF;
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u32 reg_offset = 0;
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/* Values */
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u32 dspcntr_val = dev_priv->dspcntr;
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u32 pipeconf_val = dev_priv->pipeconf;
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u32 h_active_area = mode->hdisplay;
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u32 v_active_area = mode->vdisplay;
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u32 mipi_val;
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mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX |
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TE_TRIGGER_GPIO_PIN);
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dev_dbg(dev->dev, "mipi_val =0x%x\n", mipi_val);
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dev_dbg(dev->dev, "type %s\n", (pipe == 2) ? "MIPI2" : "MIPI");
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dev_dbg(dev->dev, "h %d v %d\n", mode->hdisplay, mode->vdisplay);
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if (pipe == 2) {
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mipi_reg = MIPI_C;
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dspcntr_reg = DSPCCNTR;
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pipeconf_reg = PIPECCONF;
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reg_offset = MIPIC_REG_OFFSET;
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dspcntr_val = dev_priv->dspcntr2;
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pipeconf_val = dev_priv->pipeconf2;
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} else {
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mipi_val |= 0x2; /*two lanes for port A and C respectively*/
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}
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if (!gma_power_begin(dev, true)) {
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dev_err(dev->dev, "hw begin failed\n");
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return;
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}
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REG_WRITE(dspcntr_reg, dspcntr_val);
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REG_READ(dspcntr_reg);
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/* 20ms delay before sending exit_sleep_mode */
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msleep(20);
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/* Send exit_sleep_mode DCS */
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ret = mdfld_dsi_dbi_send_dcs(dsi_output, DCS_EXIT_SLEEP_MODE,
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NULL, 0, CMD_DATA_SRC_SYSTEM_MEM);
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if (ret) {
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dev_err(dev->dev, "sent exit_sleep_mode faild\n");
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goto out_err;
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}
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/* Send set_tear_on DCS */
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ret = mdfld_dsi_dbi_send_dcs(dsi_output, DCS_SET_TEAR_ON,
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¶m, 1, CMD_DATA_SRC_SYSTEM_MEM);
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if (ret) {
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dev_err(dev->dev, "%s - sent set_tear_on faild\n", __func__);
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goto out_err;
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}
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/* Do some init stuff */
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REG_WRITE(pipeconf_reg, pipeconf_val | PIPEACONF_DSR);
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REG_READ(pipeconf_reg);
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/* TODO: this looks ugly, try to move it to CRTC mode setting*/
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if (pipe == 2)
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dev_priv->pipeconf2 |= PIPEACONF_DSR;
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else
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dev_priv->pipeconf |= PIPEACONF_DSR;
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dev_dbg(dev->dev, "pipeconf %x\n", REG_READ(pipeconf_reg));
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ret = mdfld_dsi_dbi_update_area(dsi_output, 0, 0,
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h_active_area - 1, v_active_area - 1);
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if (ret) {
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dev_err(dev->dev, "update area failed\n");
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goto out_err;
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}
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out_err:
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gma_power_end(dev);
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if (ret)
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dev_err(dev->dev, "mode set failed\n");
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}
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static void mdfld_dsi_dbi_prepare(struct drm_encoder *encoder)
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{
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struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
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struct mdfld_dsi_dbi_output *dbi_output
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= MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
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dbi_output->mode_flags |= MODE_SETTING_IN_ENCODER;
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dbi_output->mode_flags &= ~MODE_SETTING_ENCODER_DONE;
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mdfld_dsi_dbi_set_power(encoder, false);
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}
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static void mdfld_dsi_dbi_commit(struct drm_encoder *encoder)
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{
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struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
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struct mdfld_dsi_dbi_output *dbi_output =
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MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
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struct drm_device *dev = dbi_output->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_drm_dpu_rect rect;
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mdfld_dsi_dbi_set_power(encoder, true);
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dbi_output->mode_flags &= ~MODE_SETTING_IN_ENCODER;
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rect.x = rect.y = 0;
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rect.width = 864;
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rect.height = 480;
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if (dbi_output->channel_num == 1) {
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dev_priv->dsr_fb_update |= MDFLD_DSR_2D_3D_2;
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/*if dpu enabled report a fullscreen damage*/
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mdfld_dbi_dpu_report_damage(dev, MDFLD_PLANEC, &rect);
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} else {
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dev_priv->dsr_fb_update |= MDFLD_DSR_2D_3D_0;
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mdfld_dbi_dpu_report_damage(dev, MDFLD_PLANEA, &rect);
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}
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dbi_output->mode_flags |= MODE_SETTING_ENCODER_DONE;
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}
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static void mdfld_dsi_dbi_dpms(struct drm_encoder *encoder, int mode)
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{
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struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
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struct mdfld_dsi_dbi_output *dbi_output
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= MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
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struct drm_device *dev = dbi_output->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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static bool bdispoff;
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dev_dbg(dev->dev, "%s\n", (mode == DRM_MODE_DPMS_ON ? "on" : "off"));
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if (mode == DRM_MODE_DPMS_ON) {
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/*
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* FIXME: in case I am wrong!
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* we don't need to exit dsr here to wake up plane/pipe/pll
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* if everything goes right, hw_begin will resume them all
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* during set_power.
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*/
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if (bdispoff /* FIXME && gbgfxsuspended */) {
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mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_2D_3D);
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bdispoff = false;
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dev_priv->dispstatus = true;
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}
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mdfld_dsi_dbi_set_power(encoder, true);
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/* FIXME if (gbgfxsuspended)
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gbgfxsuspended = false; */
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} else {
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/*
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* I am not sure whether this is the perfect place to
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* turn rpm on since we still have a lot of CRTC turnning
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* on work to do.
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*/
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bdispoff = true;
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dev_priv->dispstatus = false;
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mdfld_dsi_dbi_set_power(encoder, false);
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}
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}
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/*
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* Update the DBI MIPI Panel Frame Buffer.
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*/
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static void mdfld_dsi_dbi_update_fb(struct mdfld_dsi_dbi_output *dbi_output,
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int pipe)
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{
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struct mdfld_dsi_pkg_sender *sender =
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mdfld_dsi_encoder_get_pkg_sender(&dbi_output->base);
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struct drm_device *dev = dbi_output->dev;
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struct drm_crtc *crtc = dbi_output->base.base.crtc;
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struct psb_intel_crtc *psb_crtc = (crtc) ?
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to_psb_intel_crtc(crtc) : NULL;
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u32 dpll_reg = MRST_DPLL_A;
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u32 dspcntr_reg = DSPACNTR;
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u32 pipeconf_reg = PIPEACONF;
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u32 dsplinoff_reg = DSPALINOFF;
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u32 dspsurf_reg = DSPASURF;
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u32 reg_offset = 0;
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/* If mode setting on-going, back off */
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if ((dbi_output->mode_flags & MODE_SETTING_ON_GOING) ||
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(psb_crtc && psb_crtc->mode_flags & MODE_SETTING_ON_GOING) ||
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!(dbi_output->mode_flags & MODE_SETTING_ENCODER_DONE))
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return;
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if (pipe == 2) {
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dspcntr_reg = DSPCCNTR;
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pipeconf_reg = PIPECCONF;
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dsplinoff_reg = DSPCLINOFF;
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dspsurf_reg = DSPCSURF;
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reg_offset = MIPIC_REG_OFFSET;
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}
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if (!gma_power_begin(dev, true)) {
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dev_err(dev->dev, "hw begin failed\n");
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return;
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}
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/* Check DBI FIFO status */
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if (!(REG_READ(dpll_reg) & DPLL_VCO_ENABLE) ||
|
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!(REG_READ(dspcntr_reg) & DISPLAY_PLANE_ENABLE) ||
|
|
!(REG_READ(pipeconf_reg) & DISPLAY_PLANE_ENABLE))
|
|
goto update_fb_out0;
|
|
|
|
/* Refresh plane changes */
|
|
REG_WRITE(dsplinoff_reg, REG_READ(dsplinoff_reg));
|
|
REG_WRITE(dspsurf_reg, REG_READ(dspsurf_reg));
|
|
REG_READ(dspsurf_reg);
|
|
|
|
mdfld_dsi_send_dcs(sender,
|
|
DCS_WRITE_MEM_START,
|
|
NULL,
|
|
0,
|
|
CMD_DATA_SRC_PIPE,
|
|
MDFLD_DSI_SEND_PACKAGE);
|
|
|
|
dbi_output->dsr_fb_update_done = true;
|
|
update_fb_out0:
|
|
gma_power_end(dev);
|
|
}
|
|
|
|
static int tpo_cmd_get_panel_info(struct drm_device *dev,
|
|
int pipe,
|
|
struct panel_info *pi)
|
|
{
|
|
if (!dev || !pi)
|
|
return -EINVAL;
|
|
|
|
pi->width_mm = TPO_PANEL_WIDTH;
|
|
pi->height_mm = TPO_PANEL_HEIGHT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/* TPO DBI encoder helper funcs */
|
|
static const struct drm_encoder_helper_funcs mdfld_dsi_dbi_helper_funcs = {
|
|
.dpms = mdfld_dsi_dbi_dpms,
|
|
.mode_fixup = mdfld_dsi_dbi_mode_fixup,
|
|
.prepare = mdfld_dsi_dbi_prepare,
|
|
.mode_set = mdfld_dsi_dbi_mode_set,
|
|
.commit = mdfld_dsi_dbi_commit,
|
|
};
|
|
|
|
/* TPO DBI encoder funcs */
|
|
static const struct drm_encoder_funcs mdfld_dsi_dbi_encoder_funcs = {
|
|
.destroy = drm_encoder_cleanup,
|
|
};
|
|
|
|
void tpo_cmd_init(struct drm_device *dev, struct panel_funcs *p_funcs)
|
|
{
|
|
p_funcs->encoder_funcs = &mdfld_dsi_dbi_encoder_funcs;
|
|
p_funcs->encoder_helper_funcs = &mdfld_dsi_dbi_helper_funcs;
|
|
p_funcs->get_config_mode = &tpo_cmd_get_config_mode;
|
|
p_funcs->update_fb = mdfld_dsi_dbi_update_fb;
|
|
p_funcs->get_panel_info = tpo_cmd_get_panel_info;
|
|
p_funcs->reset = mdfld_dsi_panel_reset;
|
|
p_funcs->drv_ic_init = mdfld_dsi_brightness_init;
|
|
}
|