b445e26cbf
In particular, avoid membar instructions in the delay slot of a jmpl instruction. UltraSPARC-I, II, IIi, and IIe have a bug, documented in the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51 The long and short of it is that if the IMU unit misses on a branch or jmpl, and there is a store buffer synchronizing membar in the delay slot, the chip can stop fetching instructions. If interrupts are enabled or some other trap is enabled, the chip will unwedge itself, but performance will suffer. We already had a workaround for this bug in a few spots, but it's better to have the entire tree sanitized for this rule. Signed-off-by: David S. Miller <davem@davemloft.net>
255 lines
5.5 KiB
C
255 lines
5.5 KiB
C
/* $Id: semaphore.c,v 1.9 2001/11/18 00:12:56 davem Exp $
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* semaphore.c: Sparc64 semaphore implementation.
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*
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* This is basically the PPC semaphore scheme ported to use
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* the sparc64 atomic instructions, so see the PPC code for
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* credits.
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*/
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#include <linux/sched.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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/*
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* Atomically update sem->count.
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* This does the equivalent of the following:
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*
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* old_count = sem->count;
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* tmp = MAX(old_count, 0) + incr;
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* sem->count = tmp;
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* return old_count;
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*/
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static __inline__ int __sem_update_count(struct semaphore *sem, int incr)
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{
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int old_count, tmp;
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__asm__ __volatile__("\n"
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" ! __sem_update_count old_count(%0) tmp(%1) incr(%4) &sem->count(%3)\n"
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"1: ldsw [%3], %0\n"
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" mov %0, %1\n"
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" cmp %0, 0\n"
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" movl %%icc, 0, %1\n"
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" add %1, %4, %1\n"
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" cas [%3], %0, %1\n"
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" cmp %0, %1\n"
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" membar #StoreLoad | #StoreStore\n"
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" bne,pn %%icc, 1b\n"
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" nop\n"
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: "=&r" (old_count), "=&r" (tmp), "=m" (sem->count)
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: "r" (&sem->count), "r" (incr), "m" (sem->count)
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: "cc");
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return old_count;
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}
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static void __up(struct semaphore *sem)
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{
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__sem_update_count(sem, 1);
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wake_up(&sem->wait);
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}
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void up(struct semaphore *sem)
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{
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/* This atomically does:
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* old_val = sem->count;
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* new_val = sem->count + 1;
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* sem->count = new_val;
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* if (old_val < 0)
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* __up(sem);
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*
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* The (old_val < 0) test is equivalent to
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* the more straightforward (new_val <= 0),
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* but it is easier to test the former because
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* of how the CAS instruction works.
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*/
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__asm__ __volatile__("\n"
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" ! up sem(%0)\n"
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" membar #StoreLoad | #LoadLoad\n"
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"1: lduw [%0], %%g1\n"
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" add %%g1, 1, %%g7\n"
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" cas [%0], %%g1, %%g7\n"
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" cmp %%g1, %%g7\n"
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" bne,pn %%icc, 1b\n"
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" addcc %%g7, 1, %%g0\n"
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" membar #StoreLoad | #StoreStore\n"
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" ble,pn %%icc, 3f\n"
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" nop\n"
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"2:\n"
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" .subsection 2\n"
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"3: mov %0, %%g1\n"
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" save %%sp, -160, %%sp\n"
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" call %1\n"
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" mov %%g1, %%o0\n"
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" ba,pt %%xcc, 2b\n"
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" restore\n"
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" .previous\n"
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: : "r" (sem), "i" (__up)
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: "g1", "g2", "g3", "g7", "memory", "cc");
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}
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static void __sched __down(struct semaphore * sem)
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{
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struct task_struct *tsk = current;
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DECLARE_WAITQUEUE(wait, tsk);
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tsk->state = TASK_UNINTERRUPTIBLE;
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add_wait_queue_exclusive(&sem->wait, &wait);
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while (__sem_update_count(sem, -1) <= 0) {
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schedule();
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tsk->state = TASK_UNINTERRUPTIBLE;
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}
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remove_wait_queue(&sem->wait, &wait);
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tsk->state = TASK_RUNNING;
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wake_up(&sem->wait);
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}
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void __sched down(struct semaphore *sem)
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{
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might_sleep();
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/* This atomically does:
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* old_val = sem->count;
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* new_val = sem->count - 1;
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* sem->count = new_val;
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* if (old_val < 1)
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* __down(sem);
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*
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* The (old_val < 1) test is equivalent to
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* the more straightforward (new_val < 0),
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* but it is easier to test the former because
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* of how the CAS instruction works.
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*/
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__asm__ __volatile__("\n"
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" ! down sem(%0)\n"
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"1: lduw [%0], %%g1\n"
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" sub %%g1, 1, %%g7\n"
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" cas [%0], %%g1, %%g7\n"
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" cmp %%g1, %%g7\n"
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" bne,pn %%icc, 1b\n"
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" cmp %%g7, 1\n"
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" membar #StoreLoad | #StoreStore\n"
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" bl,pn %%icc, 3f\n"
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" nop\n"
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"2:\n"
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" .subsection 2\n"
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"3: mov %0, %%g1\n"
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" save %%sp, -160, %%sp\n"
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" call %1\n"
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" mov %%g1, %%o0\n"
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" ba,pt %%xcc, 2b\n"
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" restore\n"
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" .previous\n"
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: : "r" (sem), "i" (__down)
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: "g1", "g2", "g3", "g7", "memory", "cc");
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}
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int down_trylock(struct semaphore *sem)
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{
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int ret;
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/* This atomically does:
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* old_val = sem->count;
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* new_val = sem->count - 1;
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* if (old_val < 1) {
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* ret = 1;
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* } else {
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* sem->count = new_val;
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* ret = 0;
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* }
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*
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* The (old_val < 1) test is equivalent to
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* the more straightforward (new_val < 0),
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* but it is easier to test the former because
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* of how the CAS instruction works.
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*/
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__asm__ __volatile__("\n"
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" ! down_trylock sem(%1) ret(%0)\n"
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"1: lduw [%1], %%g1\n"
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" sub %%g1, 1, %%g7\n"
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" cmp %%g1, 1\n"
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" bl,pn %%icc, 2f\n"
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" mov 1, %0\n"
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" cas [%1], %%g1, %%g7\n"
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" cmp %%g1, %%g7\n"
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" bne,pn %%icc, 1b\n"
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" mov 0, %0\n"
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" membar #StoreLoad | #StoreStore\n"
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"2:\n"
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: "=&r" (ret)
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: "r" (sem)
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: "g1", "g7", "memory", "cc");
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return ret;
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}
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static int __sched __down_interruptible(struct semaphore * sem)
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{
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int retval = 0;
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struct task_struct *tsk = current;
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DECLARE_WAITQUEUE(wait, tsk);
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tsk->state = TASK_INTERRUPTIBLE;
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add_wait_queue_exclusive(&sem->wait, &wait);
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while (__sem_update_count(sem, -1) <= 0) {
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if (signal_pending(current)) {
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__sem_update_count(sem, 0);
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retval = -EINTR;
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break;
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}
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schedule();
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tsk->state = TASK_INTERRUPTIBLE;
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}
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tsk->state = TASK_RUNNING;
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remove_wait_queue(&sem->wait, &wait);
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wake_up(&sem->wait);
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return retval;
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}
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int __sched down_interruptible(struct semaphore *sem)
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{
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int ret = 0;
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might_sleep();
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/* This atomically does:
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* old_val = sem->count;
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* new_val = sem->count - 1;
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* sem->count = new_val;
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* if (old_val < 1)
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* ret = __down_interruptible(sem);
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*
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* The (old_val < 1) test is equivalent to
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* the more straightforward (new_val < 0),
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* but it is easier to test the former because
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* of how the CAS instruction works.
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*/
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__asm__ __volatile__("\n"
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" ! down_interruptible sem(%2) ret(%0)\n"
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"1: lduw [%2], %%g1\n"
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" sub %%g1, 1, %%g7\n"
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" cas [%2], %%g1, %%g7\n"
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" cmp %%g1, %%g7\n"
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" bne,pn %%icc, 1b\n"
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" cmp %%g7, 1\n"
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" membar #StoreLoad | #StoreStore\n"
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" bl,pn %%icc, 3f\n"
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" nop\n"
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"2:\n"
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" .subsection 2\n"
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"3: mov %2, %%g1\n"
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" save %%sp, -160, %%sp\n"
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" call %3\n"
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" mov %%g1, %%o0\n"
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" ba,pt %%xcc, 2b\n"
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" restore\n"
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" .previous\n"
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: "=r" (ret)
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: "0" (ret), "r" (sem), "i" (__down_interruptible)
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: "g1", "g2", "g3", "g7", "memory", "cc");
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return ret;
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}
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