52eba8dd5e
The core/mem/shader clocks don't support the fractional feedback divider, causing our calculated clocks to be off by quite a lot in some cases. To solve this we will switch to a search-based algorithm when fN is NULL. For my NVA8 at PL3, this actually generates identical cooefficients to the binary driver. Hopefully that's a good sign, and that does not break VPLL calculation for someone.. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
97 lines
2.6 KiB
C
97 lines
2.6 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_hw.h"
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int
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nv50_calc_pll(struct drm_device *dev, struct pll_lims *pll, int clk,
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int *N1, int *M1, int *N2, int *M2, int *P)
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{
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struct nouveau_pll_vals pll_vals;
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int ret;
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ret = nouveau_calc_pll_mnp(dev, pll, clk, &pll_vals);
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if (ret <= 0)
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return ret;
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*N1 = pll_vals.N1;
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*M1 = pll_vals.M1;
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*N2 = pll_vals.N2;
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*M2 = pll_vals.M2;
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*P = pll_vals.log2P;
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return ret;
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}
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int
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nva3_calc_pll(struct drm_device *dev, struct pll_lims *pll, int clk,
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int *pN, int *pfN, int *pM, int *P)
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{
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u32 best_err = ~0, err;
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int M, lM, hM, N, fN;
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*P = pll->vco1.maxfreq / clk;
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if (*P > pll->max_p)
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*P = pll->max_p;
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if (*P < pll->min_p)
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*P = pll->min_p;
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lM = (pll->refclk + pll->vco1.max_inputfreq) / pll->vco1.max_inputfreq;
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lM = max(lM, (int)pll->vco1.min_m);
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hM = (pll->refclk + pll->vco1.min_inputfreq) / pll->vco1.min_inputfreq;
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hM = min(hM, (int)pll->vco1.max_m);
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for (M = lM; M <= hM; M++) {
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u32 tmp = clk * *P * M;
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N = tmp / pll->refclk;
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fN = tmp % pll->refclk;
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if (!pfN && fN >= pll->refclk / 2)
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N++;
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if (N < pll->vco1.min_n)
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continue;
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if (N > pll->vco1.max_n)
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break;
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err = abs(clk - (pll->refclk * N / M / *P));
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if (err < best_err) {
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best_err = err;
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*pN = N;
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*pM = M;
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}
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if (pfN) {
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*pfN = (((fN << 13) / pll->refclk) - 4096) & 0xffff;
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return clk;
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}
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}
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if (unlikely(best_err == ~0)) {
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NV_ERROR(dev, "unable to find matching pll values\n");
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return -EINVAL;
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}
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return pll->refclk * *pN / *pM / *P;
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}
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