23bdf86aa0
Patch from Lennert Buytenhek This patch adds support for the new XScale v3 core. This is an ARMv5 ISA core with the following additions: - L2 cache - I/O coherency support (on select chipsets) - Low-Locality Reference cache attributes (replaces mini-cache) - Supersections (v6 compatible) - 36-bit addressing (v6 compatible) - Single instruction cache line clean/invalidate - LRU cache replacement (vs round-robin) I attempted to merge the XSC3 support into proc-xscale.S, but XSC3 cores have separate errata and have to handle things like L2, so it is simpler to keep it separate. L2 cache support is currently a build option because the L2 enable bit must be set before we enable the MMU and there is no easy way to capture command line parameters at this point. There are still optimizations that can be done such as using LLR for copypage (in theory using the exisiting mini-cache code) but those can be addressed down the road. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
646 lines
16 KiB
C
646 lines
16 KiB
C
/*
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* linux/arch/arm/mm/mm-armv.c
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*
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* Copyright (C) 1998-2005 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Page table sludge for ARM v3 and v4 processor architectures.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/highmem.h>
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#include <linux/nodemask.h>
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#include <asm/pgalloc.h>
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#include <asm/page.h>
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#include <asm/setup.h>
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#include <asm/tlbflush.h>
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#include <asm/mach/map.h>
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#define CPOLICY_UNCACHED 0
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#define CPOLICY_BUFFERED 1
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#define CPOLICY_WRITETHROUGH 2
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#define CPOLICY_WRITEBACK 3
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#define CPOLICY_WRITEALLOC 4
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static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
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static unsigned int ecc_mask __initdata = 0;
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pgprot_t pgprot_kernel;
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EXPORT_SYMBOL(pgprot_kernel);
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pmd_t *top_pmd;
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struct cachepolicy {
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const char policy[16];
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unsigned int cr_mask;
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unsigned int pmd;
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unsigned int pte;
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};
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static struct cachepolicy cache_policies[] __initdata = {
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{
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.policy = "uncached",
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.cr_mask = CR_W|CR_C,
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.pmd = PMD_SECT_UNCACHED,
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.pte = 0,
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}, {
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.policy = "buffered",
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.cr_mask = CR_C,
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.pmd = PMD_SECT_BUFFERED,
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.pte = PTE_BUFFERABLE,
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}, {
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.policy = "writethrough",
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.cr_mask = 0,
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.pmd = PMD_SECT_WT,
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.pte = PTE_CACHEABLE,
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}, {
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.policy = "writeback",
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.cr_mask = 0,
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.pmd = PMD_SECT_WB,
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.pte = PTE_BUFFERABLE|PTE_CACHEABLE,
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}, {
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.policy = "writealloc",
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.cr_mask = 0,
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.pmd = PMD_SECT_WBWA,
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.pte = PTE_BUFFERABLE|PTE_CACHEABLE,
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}
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};
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/*
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* These are useful for identifing cache coherency
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* problems by allowing the cache or the cache and
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* writebuffer to be turned off. (Note: the write
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* buffer should not be on and the cache off).
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*/
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static void __init early_cachepolicy(char **p)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
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int len = strlen(cache_policies[i].policy);
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if (memcmp(*p, cache_policies[i].policy, len) == 0) {
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cachepolicy = i;
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cr_alignment &= ~cache_policies[i].cr_mask;
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cr_no_alignment &= ~cache_policies[i].cr_mask;
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*p += len;
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break;
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}
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}
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if (i == ARRAY_SIZE(cache_policies))
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printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
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flush_cache_all();
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set_cr(cr_alignment);
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}
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static void __init early_nocache(char **__unused)
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{
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char *p = "buffered";
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printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
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early_cachepolicy(&p);
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}
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static void __init early_nowrite(char **__unused)
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{
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char *p = "uncached";
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printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
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early_cachepolicy(&p);
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}
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static void __init early_ecc(char **p)
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{
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if (memcmp(*p, "on", 2) == 0) {
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ecc_mask = PMD_PROTECTION;
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*p += 2;
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} else if (memcmp(*p, "off", 3) == 0) {
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ecc_mask = 0;
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*p += 3;
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}
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}
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__early_param("nocache", early_nocache);
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__early_param("nowb", early_nowrite);
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__early_param("cachepolicy=", early_cachepolicy);
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__early_param("ecc=", early_ecc);
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static int __init noalign_setup(char *__unused)
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{
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cr_alignment &= ~CR_A;
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cr_no_alignment &= ~CR_A;
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set_cr(cr_alignment);
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return 1;
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}
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__setup("noalign", noalign_setup);
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#define FIRST_KERNEL_PGD_NR (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD)
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static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt)
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{
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return pmd_offset(pgd, virt);
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}
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static inline pmd_t *pmd_off_k(unsigned long virt)
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{
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return pmd_off(pgd_offset_k(virt), virt);
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}
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/*
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* need to get a 16k page for level 1
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*/
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pgd_t *get_pgd_slow(struct mm_struct *mm)
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{
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pgd_t *new_pgd, *init_pgd;
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pmd_t *new_pmd, *init_pmd;
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pte_t *new_pte, *init_pte;
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new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 2);
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if (!new_pgd)
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goto no_pgd;
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memzero(new_pgd, FIRST_KERNEL_PGD_NR * sizeof(pgd_t));
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/*
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* Copy over the kernel and IO PGD entries
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*/
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init_pgd = pgd_offset_k(0);
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memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR,
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(PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t));
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clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t));
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if (!vectors_high()) {
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/*
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* On ARM, first page must always be allocated since it
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* contains the machine vectors.
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*/
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new_pmd = pmd_alloc(mm, new_pgd, 0);
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if (!new_pmd)
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goto no_pmd;
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new_pte = pte_alloc_map(mm, new_pmd, 0);
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if (!new_pte)
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goto no_pte;
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init_pmd = pmd_offset(init_pgd, 0);
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init_pte = pte_offset_map_nested(init_pmd, 0);
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set_pte(new_pte, *init_pte);
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pte_unmap_nested(init_pte);
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pte_unmap(new_pte);
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}
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return new_pgd;
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no_pte:
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pmd_free(new_pmd);
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no_pmd:
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free_pages((unsigned long)new_pgd, 2);
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no_pgd:
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return NULL;
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}
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void free_pgd_slow(pgd_t *pgd)
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{
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pmd_t *pmd;
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struct page *pte;
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if (!pgd)
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return;
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/* pgd is always present and good */
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pmd = pmd_off(pgd, 0);
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if (pmd_none(*pmd))
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goto free;
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if (pmd_bad(*pmd)) {
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pmd_ERROR(*pmd);
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pmd_clear(pmd);
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goto free;
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}
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pte = pmd_page(*pmd);
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pmd_clear(pmd);
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dec_page_state(nr_page_table_pages);
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pte_lock_deinit(pte);
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pte_free(pte);
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pmd_free(pmd);
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free:
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free_pages((unsigned long) pgd, 2);
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}
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/*
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* Create a SECTION PGD between VIRT and PHYS in domain
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* DOMAIN with protection PROT. This operates on half-
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* pgdir entry increments.
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*/
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static inline void
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alloc_init_section(unsigned long virt, unsigned long phys, int prot)
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{
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pmd_t *pmdp = pmd_off_k(virt);
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if (virt & (1 << 20))
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pmdp++;
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*pmdp = __pmd(phys | prot);
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flush_pmd_entry(pmdp);
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}
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/*
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* Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT
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*/
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static inline void
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alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
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{
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int i;
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for (i = 0; i < 16; i += 1) {
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alloc_init_section(virt, phys, prot | PMD_SECT_SUPER);
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virt += (PGDIR_SIZE / 2);
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}
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}
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/*
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* Add a PAGE mapping between VIRT and PHYS in domain
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* DOMAIN with protection PROT. Note that due to the
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* way we map the PTEs, we must allocate two PTE_SIZE'd
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* blocks - one for the Linux pte table, and one for
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* the hardware pte table.
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*/
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static inline void
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alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot)
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{
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pmd_t *pmdp = pmd_off_k(virt);
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pte_t *ptep;
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if (pmd_none(*pmdp)) {
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ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
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sizeof(pte_t));
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__pmd_populate(pmdp, __pa(ptep) | prot_l1);
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}
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ptep = pte_offset_kernel(pmdp, virt);
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set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
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}
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struct mem_types {
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unsigned int prot_pte;
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unsigned int prot_l1;
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unsigned int prot_sect;
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unsigned int domain;
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};
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static struct mem_types mem_types[] __initdata = {
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[MT_DEVICE] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_WRITE,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED |
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PMD_SECT_AP_WRITE,
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.domain = DOMAIN_IO,
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},
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[MT_CACHECLEAN] = {
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.prot_sect = PMD_TYPE_SECT,
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.domain = DOMAIN_KERNEL,
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},
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[MT_MINICLEAN] = {
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_MINICACHE,
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.domain = DOMAIN_KERNEL,
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},
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[MT_LOW_VECTORS] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_EXEC,
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.prot_l1 = PMD_TYPE_TABLE,
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.domain = DOMAIN_USER,
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},
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[MT_HIGH_VECTORS] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_USER | L_PTE_EXEC,
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.prot_l1 = PMD_TYPE_TABLE,
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.domain = DOMAIN_USER,
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},
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[MT_MEMORY] = {
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
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.domain = DOMAIN_KERNEL,
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},
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[MT_ROM] = {
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.prot_sect = PMD_TYPE_SECT,
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.domain = DOMAIN_KERNEL,
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},
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[MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_WRITE,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED |
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PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
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PMD_SECT_TEX(1),
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.domain = DOMAIN_IO,
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},
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[MT_NONSHARED_DEVICE] = {
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_NONSHARED_DEV |
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PMD_SECT_AP_WRITE,
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.domain = DOMAIN_IO,
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}
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};
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/*
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* Adjust the PMD section entries according to the CPU in use.
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*/
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void __init build_mem_type_table(void)
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{
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struct cachepolicy *cp;
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unsigned int cr = get_cr();
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unsigned int user_pgprot, kern_pgprot;
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int cpu_arch = cpu_architecture();
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int i;
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#if defined(CONFIG_CPU_DCACHE_DISABLE)
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if (cachepolicy > CPOLICY_BUFFERED)
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cachepolicy = CPOLICY_BUFFERED;
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#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
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if (cachepolicy > CPOLICY_WRITETHROUGH)
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cachepolicy = CPOLICY_WRITETHROUGH;
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#endif
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if (cpu_arch < CPU_ARCH_ARMv5) {
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if (cachepolicy >= CPOLICY_WRITEALLOC)
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cachepolicy = CPOLICY_WRITEBACK;
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ecc_mask = 0;
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}
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if (cpu_arch <= CPU_ARCH_ARMv5TEJ) {
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for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
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if (mem_types[i].prot_l1)
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mem_types[i].prot_l1 |= PMD_BIT4;
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if (mem_types[i].prot_sect)
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mem_types[i].prot_sect |= PMD_BIT4;
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}
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}
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cp = &cache_policies[cachepolicy];
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kern_pgprot = user_pgprot = cp->pte;
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/*
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* ARMv6 and above have extended page tables.
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*/
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if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
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/*
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* bit 4 becomes XN which we must clear for the
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* kernel memory mapping.
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*/
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mem_types[MT_MEMORY].prot_sect &= ~PMD_BIT4;
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mem_types[MT_ROM].prot_sect &= ~PMD_BIT4;
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/*
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* Mark cache clean areas and XIP ROM read only
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* from SVC mode and no access from userspace.
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*/
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mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
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mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
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mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
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/*
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* Mark the device area as "shared device"
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*/
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mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
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mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
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/*
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* User pages need to be mapped with the ASID
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* (iow, non-global)
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*/
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user_pgprot |= L_PTE_ASID;
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#ifdef CONFIG_SMP
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/*
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* Mark memory with the "shared" attribute for SMP systems
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*/
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user_pgprot |= L_PTE_SHARED;
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kern_pgprot |= L_PTE_SHARED;
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mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
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#endif
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}
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for (i = 0; i < 16; i++) {
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unsigned long v = pgprot_val(protection_map[i]);
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v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
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protection_map[i] = __pgprot(v);
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}
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mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
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mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
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if (cpu_arch >= CPU_ARCH_ARMv5) {
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#ifndef CONFIG_SMP
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/*
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* Only use write-through for non-SMP systems
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*/
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mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
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mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
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#endif
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} else {
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mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
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}
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pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
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L_PTE_DIRTY | L_PTE_WRITE |
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L_PTE_EXEC | kern_pgprot);
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mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
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mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
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mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
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mem_types[MT_ROM].prot_sect |= cp->pmd;
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switch (cp->pmd) {
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case PMD_SECT_WT:
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mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
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break;
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case PMD_SECT_WB:
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case PMD_SECT_WBWA:
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mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
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break;
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}
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printk("Memory policy: ECC %sabled, Data cache %s\n",
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ecc_mask ? "en" : "dis", cp->policy);
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}
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#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
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/*
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* Create the page directory entries and any necessary
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* page tables for the mapping specified by `md'. We
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* are able to cope here with varying sizes and address
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* offsets, and we take full advantage of sections and
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|
* supersections.
|
|
*/
|
|
void __init create_mapping(struct map_desc *md)
|
|
{
|
|
unsigned long virt, length;
|
|
int prot_sect, prot_l1, domain;
|
|
pgprot_t prot_pte;
|
|
unsigned long off = (u32)__pfn_to_phys(md->pfn);
|
|
|
|
if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
|
|
printk(KERN_WARNING "BUG: not creating mapping for "
|
|
"0x%08llx at 0x%08lx in user region\n",
|
|
__pfn_to_phys((u64)md->pfn), md->virtual);
|
|
return;
|
|
}
|
|
|
|
if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
|
|
md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
|
|
printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
|
|
"overlaps vmalloc space\n",
|
|
__pfn_to_phys((u64)md->pfn), md->virtual);
|
|
}
|
|
|
|
domain = mem_types[md->type].domain;
|
|
prot_pte = __pgprot(mem_types[md->type].prot_pte);
|
|
prot_l1 = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain);
|
|
prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain);
|
|
|
|
/*
|
|
* Catch 36-bit addresses
|
|
*/
|
|
if(md->pfn >= 0x100000) {
|
|
if(domain) {
|
|
printk(KERN_ERR "MM: invalid domain in supersection "
|
|
"mapping for 0x%08llx at 0x%08lx\n",
|
|
__pfn_to_phys((u64)md->pfn), md->virtual);
|
|
return;
|
|
}
|
|
if((md->virtual | md->length | __pfn_to_phys(md->pfn))
|
|
& ~SUPERSECTION_MASK) {
|
|
printk(KERN_ERR "MM: cannot create mapping for "
|
|
"0x%08llx at 0x%08lx invalid alignment\n",
|
|
__pfn_to_phys((u64)md->pfn), md->virtual);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Shift bits [35:32] of address into bits [23:20] of PMD
|
|
* (See ARMv6 spec).
|
|
*/
|
|
off |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
|
|
}
|
|
|
|
virt = md->virtual;
|
|
off -= virt;
|
|
length = md->length;
|
|
|
|
if (mem_types[md->type].prot_l1 == 0 &&
|
|
(virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
|
|
printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
|
|
"be mapped using pages, ignoring.\n",
|
|
__pfn_to_phys(md->pfn), md->virtual);
|
|
return;
|
|
}
|
|
|
|
while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
|
|
alloc_init_page(virt, virt + off, prot_l1, prot_pte);
|
|
|
|
virt += PAGE_SIZE;
|
|
length -= PAGE_SIZE;
|
|
}
|
|
|
|
/* N.B. ARMv6 supersections are only defined to work with domain 0.
|
|
* Since domain assignments can in fact be arbitrary, the
|
|
* 'domain == 0' check below is required to insure that ARMv6
|
|
* supersections are only allocated for domain 0 regardless
|
|
* of the actual domain assignments in use.
|
|
*/
|
|
if ((cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())
|
|
&& domain == 0) {
|
|
/*
|
|
* Align to supersection boundary if !high pages.
|
|
* High pages have already been checked for proper
|
|
* alignment above and they will fail the SUPSERSECTION_MASK
|
|
* check because of the way the address is encoded into
|
|
* offset.
|
|
*/
|
|
if (md->pfn <= 0x100000) {
|
|
while ((virt & ~SUPERSECTION_MASK ||
|
|
(virt + off) & ~SUPERSECTION_MASK) &&
|
|
length >= (PGDIR_SIZE / 2)) {
|
|
alloc_init_section(virt, virt + off, prot_sect);
|
|
|
|
virt += (PGDIR_SIZE / 2);
|
|
length -= (PGDIR_SIZE / 2);
|
|
}
|
|
}
|
|
|
|
while (length >= SUPERSECTION_SIZE) {
|
|
alloc_init_supersection(virt, virt + off, prot_sect);
|
|
|
|
virt += SUPERSECTION_SIZE;
|
|
length -= SUPERSECTION_SIZE;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* A section mapping covers half a "pgdir" entry.
|
|
*/
|
|
while (length >= (PGDIR_SIZE / 2)) {
|
|
alloc_init_section(virt, virt + off, prot_sect);
|
|
|
|
virt += (PGDIR_SIZE / 2);
|
|
length -= (PGDIR_SIZE / 2);
|
|
}
|
|
|
|
while (length >= PAGE_SIZE) {
|
|
alloc_init_page(virt, virt + off, prot_l1, prot_pte);
|
|
|
|
virt += PAGE_SIZE;
|
|
length -= PAGE_SIZE;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* In order to soft-boot, we need to insert a 1:1 mapping in place of
|
|
* the user-mode pages. This will then ensure that we have predictable
|
|
* results when turning the mmu off
|
|
*/
|
|
void setup_mm_for_reboot(char mode)
|
|
{
|
|
unsigned long base_pmdval;
|
|
pgd_t *pgd;
|
|
int i;
|
|
|
|
if (current->mm && current->mm->pgd)
|
|
pgd = current->mm->pgd;
|
|
else
|
|
pgd = init_mm.pgd;
|
|
|
|
base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
|
|
if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ)
|
|
base_pmdval |= PMD_BIT4;
|
|
|
|
for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
|
|
unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
|
|
pmd_t *pmd;
|
|
|
|
pmd = pmd_off(pgd, i << PGDIR_SHIFT);
|
|
pmd[0] = __pmd(pmdval);
|
|
pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
|
|
flush_pmd_entry(pmd);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Create the architecture specific mappings
|
|
*/
|
|
void __init iotable_init(struct map_desc *io_desc, int nr)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < nr; i++)
|
|
create_mapping(io_desc + i);
|
|
}
|