3e9957b486
The 'size' variable contains the correct register size for both AR7 and Titan, but we never used it to ioremap the correct register size. This problem only shows up on Titan. [ralf@linux-mips.org: Fixed the fix. The original patch as in patchwork recognizes the problem correctly then fails to fix it ...] Reported-by: Alexander Clouter <alex@digriz.org.uk> Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/2380/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
348 lines
8.2 KiB
C
348 lines
8.2 KiB
C
/*
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* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
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* Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/module.h>
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#include <linux/gpio.h>
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#include <asm/mach-ar7/gpio.h>
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struct ar7_gpio_chip {
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void __iomem *regs;
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struct gpio_chip chip;
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};
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static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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{
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struct ar7_gpio_chip *gpch =
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container_of(chip, struct ar7_gpio_chip, chip);
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void __iomem *gpio_in = gpch->regs + AR7_GPIO_INPUT;
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return readl(gpio_in) & (1 << gpio);
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}
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static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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{
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struct ar7_gpio_chip *gpch =
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container_of(chip, struct ar7_gpio_chip, chip);
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void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;
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void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;
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return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
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}
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static void ar7_gpio_set_value(struct gpio_chip *chip,
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unsigned gpio, int value)
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{
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struct ar7_gpio_chip *gpch =
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container_of(chip, struct ar7_gpio_chip, chip);
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void __iomem *gpio_out = gpch->regs + AR7_GPIO_OUTPUT;
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unsigned tmp;
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tmp = readl(gpio_out) & ~(1 << gpio);
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if (value)
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tmp |= 1 << gpio;
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writel(tmp, gpio_out);
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}
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static void titan_gpio_set_value(struct gpio_chip *chip,
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unsigned gpio, int value)
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{
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struct ar7_gpio_chip *gpch =
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container_of(chip, struct ar7_gpio_chip, chip);
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void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;
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void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;
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unsigned tmp;
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tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
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if (value)
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tmp |= 1 << (gpio & 0x1f);
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writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
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}
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static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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struct ar7_gpio_chip *gpch =
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container_of(chip, struct ar7_gpio_chip, chip);
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void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
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writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
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return 0;
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}
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static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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struct ar7_gpio_chip *gpch =
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container_of(chip, struct ar7_gpio_chip, chip);
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void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
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void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
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if (gpio >= TITAN_GPIO_MAX)
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return -EINVAL;
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writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
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gpio >> 5 ? gpio_dir1 : gpio_dir0);
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return 0;
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}
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static int ar7_gpio_direction_output(struct gpio_chip *chip,
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unsigned gpio, int value)
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{
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struct ar7_gpio_chip *gpch =
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container_of(chip, struct ar7_gpio_chip, chip);
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void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
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ar7_gpio_set_value(chip, gpio, value);
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writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
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return 0;
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}
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static int titan_gpio_direction_output(struct gpio_chip *chip,
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unsigned gpio, int value)
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{
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struct ar7_gpio_chip *gpch =
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container_of(chip, struct ar7_gpio_chip, chip);
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void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
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void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
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if (gpio >= TITAN_GPIO_MAX)
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return -EINVAL;
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titan_gpio_set_value(chip, gpio, value);
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writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
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(gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
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return 0;
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}
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static struct ar7_gpio_chip ar7_gpio_chip = {
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.chip = {
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.label = "ar7-gpio",
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.direction_input = ar7_gpio_direction_input,
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.direction_output = ar7_gpio_direction_output,
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.set = ar7_gpio_set_value,
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.get = ar7_gpio_get_value,
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.base = 0,
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.ngpio = AR7_GPIO_MAX,
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}
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};
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static struct ar7_gpio_chip titan_gpio_chip = {
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.chip = {
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.label = "titan-gpio",
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.direction_input = titan_gpio_direction_input,
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.direction_output = titan_gpio_direction_output,
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.set = titan_gpio_set_value,
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.get = titan_gpio_get_value,
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.base = 0,
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.ngpio = TITAN_GPIO_MAX,
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}
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};
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static inline int ar7_gpio_enable_ar7(unsigned gpio)
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{
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void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
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writel(readl(gpio_en) | (1 << gpio), gpio_en);
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return 0;
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}
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static inline int ar7_gpio_enable_titan(unsigned gpio)
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{
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void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
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void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
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writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
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gpio >> 5 ? gpio_en1 : gpio_en0);
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return 0;
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}
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int ar7_gpio_enable(unsigned gpio)
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{
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return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
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ar7_gpio_enable_ar7(gpio);
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}
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EXPORT_SYMBOL(ar7_gpio_enable);
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static inline int ar7_gpio_disable_ar7(unsigned gpio)
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{
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void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
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writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
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return 0;
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}
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static inline int ar7_gpio_disable_titan(unsigned gpio)
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{
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void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
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void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
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writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
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gpio >> 5 ? gpio_en1 : gpio_en0);
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return 0;
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}
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int ar7_gpio_disable(unsigned gpio)
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{
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return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
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ar7_gpio_disable_ar7(gpio);
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}
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EXPORT_SYMBOL(ar7_gpio_disable);
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struct titan_gpio_cfg {
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u32 reg;
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u32 shift;
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u32 func;
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};
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static struct titan_gpio_cfg titan_gpio_table[] = {
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/* reg, start bit, mux value */
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{4, 24, 1},
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{4, 26, 1},
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{4, 28, 1},
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{4, 30, 1},
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{5, 6, 1},
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{5, 8, 1},
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{5, 10, 1},
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{5, 12, 1},
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{7, 14, 3},
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{7, 16, 3},
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{7, 18, 3},
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{7, 20, 3},
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{7, 22, 3},
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{7, 26, 3},
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{7, 28, 3},
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{7, 30, 3},
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{8, 0, 3},
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{8, 2, 3},
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{8, 4, 3},
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{8, 10, 3},
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{8, 14, 3},
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{8, 16, 3},
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{8, 18, 3},
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{8, 20, 3},
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{9, 8, 3},
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{9, 10, 3},
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{9, 12, 3},
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{9, 14, 3},
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{9, 18, 3},
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{9, 20, 3},
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{9, 24, 3},
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{9, 26, 3},
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{9, 28, 3},
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{9, 30, 3},
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{10, 0, 3},
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{10, 2, 3},
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{10, 8, 3},
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{10, 10, 3},
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{10, 12, 3},
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{10, 14, 3},
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{13, 12, 3},
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{13, 14, 3},
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{13, 16, 3},
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{13, 18, 3},
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{13, 24, 3},
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{13, 26, 3},
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{13, 28, 3},
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{13, 30, 3},
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{14, 2, 3},
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{14, 6, 3},
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{14, 8, 3},
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{14, 12, 3}
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};
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static int titan_gpio_pinsel(unsigned gpio)
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{
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struct titan_gpio_cfg gpio_cfg;
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u32 mux_status, pin_sel_reg, tmp;
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void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);
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if (gpio >= ARRAY_SIZE(titan_gpio_table))
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return -EINVAL;
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gpio_cfg = titan_gpio_table[gpio];
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pin_sel_reg = gpio_cfg.reg - 1;
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mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;
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/* Check the mux status */
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if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))
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return 0;
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/* Set the pin sel value */
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tmp = readl(pin_sel + pin_sel_reg);
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tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
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writel(tmp, pin_sel + pin_sel_reg);
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return 0;
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}
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/* Perform minimal Titan GPIO configuration */
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static void titan_gpio_init(void)
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{
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unsigned i;
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for (i = 44; i < 48; i++) {
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titan_gpio_pinsel(i);
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ar7_gpio_enable_titan(i);
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titan_gpio_direction_input(&titan_gpio_chip.chip, i);
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}
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}
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int __init ar7_gpio_init(void)
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{
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int ret;
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struct ar7_gpio_chip *gpch;
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unsigned size;
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if (!ar7_is_titan()) {
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gpch = &ar7_gpio_chip;
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size = 0x10;
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} else {
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gpch = &titan_gpio_chip;
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size = 0x1f;
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}
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gpch->regs = ioremap_nocache(AR7_REGS_GPIO, size);
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if (!gpch->regs) {
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printk(KERN_ERR "%s: failed to ioremap regs\n",
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gpch->chip.label);
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return -ENOMEM;
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}
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ret = gpiochip_add(&gpch->chip);
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if (ret) {
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printk(KERN_ERR "%s: failed to add gpiochip\n",
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gpch->chip.label);
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return ret;
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}
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printk(KERN_INFO "%s: registered %d GPIOs\n",
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gpch->chip.label, gpch->chip.ngpio);
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if (ar7_is_titan())
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titan_gpio_init();
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return ret;
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}
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