0f18e719dc
This requires us to do a sort-of fake dcr_map(), so that base is set properly. This will be fixed/removed when the device-tree-aware emac driver is merged. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Jeff Garzik <jeff@garzik.org>
570 lines
15 KiB
C
570 lines
15 KiB
C
/*
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* drivers/net/ibm_emac/ibm_emac_mal.c
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*
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* Memory Access Layer (MAL) support
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*
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* Copyright (c) 2004, 2005 Zultys Technologies.
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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*
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* Based on original work by
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* Benjamin Herrenschmidt <benh@kernel.crashing.org>,
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* David Gibson <hermes@gibson.dropbear.id.au>,
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*
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* Armin Kuster <akuster@mvista.com>
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* Copyright 2002 MontaVista Softare Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/netdevice.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <asm/ocp.h>
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#include "ibm_emac_core.h"
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#include "ibm_emac_mal.h"
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#include "ibm_emac_debug.h"
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int __init mal_register_commac(struct ibm_ocp_mal *mal,
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struct mal_commac *commac)
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{
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unsigned long flags;
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local_irq_save(flags);
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MAL_DBG("%d: reg(%08x, %08x)" NL, mal->def->index,
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commac->tx_chan_mask, commac->rx_chan_mask);
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/* Don't let multiple commacs claim the same channel(s) */
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if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
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(mal->rx_chan_mask & commac->rx_chan_mask)) {
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local_irq_restore(flags);
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printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
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mal->def->index);
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return -EBUSY;
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}
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mal->tx_chan_mask |= commac->tx_chan_mask;
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mal->rx_chan_mask |= commac->rx_chan_mask;
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list_add(&commac->list, &mal->list);
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local_irq_restore(flags);
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return 0;
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}
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void mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac)
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{
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unsigned long flags;
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local_irq_save(flags);
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MAL_DBG("%d: unreg(%08x, %08x)" NL, mal->def->index,
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commac->tx_chan_mask, commac->rx_chan_mask);
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mal->tx_chan_mask &= ~commac->tx_chan_mask;
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mal->rx_chan_mask &= ~commac->rx_chan_mask;
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list_del_init(&commac->list);
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local_irq_restore(flags);
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}
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int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size)
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{
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struct ocp_func_mal_data *maldata = mal->def->additions;
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BUG_ON(channel < 0 || channel >= maldata->num_rx_chans ||
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size > MAL_MAX_RX_SIZE);
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MAL_DBG("%d: set_rbcs(%d, %lu)" NL, mal->def->index, channel, size);
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if (size & 0xf) {
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printk(KERN_WARNING
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"mal%d: incorrect RX size %lu for the channel %d\n",
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mal->def->index, size, channel);
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return -EINVAL;
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}
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set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
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return 0;
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}
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int mal_tx_bd_offset(struct ibm_ocp_mal *mal, int channel)
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{
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struct ocp_func_mal_data *maldata = mal->def->additions;
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BUG_ON(channel < 0 || channel >= maldata->num_tx_chans);
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return channel * NUM_TX_BUFF;
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}
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int mal_rx_bd_offset(struct ibm_ocp_mal *mal, int channel)
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{
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struct ocp_func_mal_data *maldata = mal->def->additions;
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BUG_ON(channel < 0 || channel >= maldata->num_rx_chans);
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return maldata->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
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}
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void mal_enable_tx_channel(struct ibm_ocp_mal *mal, int channel)
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{
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local_bh_disable();
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MAL_DBG("%d: enable_tx(%d)" NL, mal->def->index, channel);
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set_mal_dcrn(mal, MAL_TXCASR,
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get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
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local_bh_enable();
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}
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void mal_disable_tx_channel(struct ibm_ocp_mal *mal, int channel)
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{
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set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
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MAL_DBG("%d: disable_tx(%d)" NL, mal->def->index, channel);
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}
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void mal_enable_rx_channel(struct ibm_ocp_mal *mal, int channel)
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{
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local_bh_disable();
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MAL_DBG("%d: enable_rx(%d)" NL, mal->def->index, channel);
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set_mal_dcrn(mal, MAL_RXCASR,
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get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
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local_bh_enable();
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}
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void mal_disable_rx_channel(struct ibm_ocp_mal *mal, int channel)
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{
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set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
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MAL_DBG("%d: disable_rx(%d)" NL, mal->def->index, channel);
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}
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void mal_poll_add(struct ibm_ocp_mal *mal, struct mal_commac *commac)
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{
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local_bh_disable();
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MAL_DBG("%d: poll_add(%p)" NL, mal->def->index, commac);
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list_add_tail(&commac->poll_list, &mal->poll_list);
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local_bh_enable();
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}
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void mal_poll_del(struct ibm_ocp_mal *mal, struct mal_commac *commac)
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{
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local_bh_disable();
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MAL_DBG("%d: poll_del(%p)" NL, mal->def->index, commac);
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list_del(&commac->poll_list);
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local_bh_enable();
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}
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/* synchronized by mal_poll() */
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static inline void mal_enable_eob_irq(struct ibm_ocp_mal *mal)
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{
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MAL_DBG2("%d: enable_irq" NL, mal->def->index);
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set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
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}
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/* synchronized by __LINK_STATE_RX_SCHED bit in ndev->state */
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static inline void mal_disable_eob_irq(struct ibm_ocp_mal *mal)
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{
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set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
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MAL_DBG2("%d: disable_irq" NL, mal->def->index);
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}
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static irqreturn_t mal_serr(int irq, void *dev_instance)
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{
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struct ibm_ocp_mal *mal = dev_instance;
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u32 esr = get_mal_dcrn(mal, MAL_ESR);
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/* Clear the error status register */
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set_mal_dcrn(mal, MAL_ESR, esr);
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MAL_DBG("%d: SERR %08x" NL, mal->def->index, esr);
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if (esr & MAL_ESR_EVB) {
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if (esr & MAL_ESR_DE) {
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/* We ignore Descriptor error,
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* TXDE or RXDE interrupt will be generated anyway.
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*/
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return IRQ_HANDLED;
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}
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if (esr & MAL_ESR_PEIN) {
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/* PLB error, it's probably buggy hardware or
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* incorrect physical address in BD (i.e. bug)
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*/
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if (net_ratelimit())
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printk(KERN_ERR
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"mal%d: system error, PLB (ESR = 0x%08x)\n",
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mal->def->index, esr);
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return IRQ_HANDLED;
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}
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/* OPB error, it's probably buggy hardware or incorrect EBC setup */
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if (net_ratelimit())
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printk(KERN_ERR
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"mal%d: system error, OPB (ESR = 0x%08x)\n",
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mal->def->index, esr);
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}
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return IRQ_HANDLED;
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}
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static inline void mal_schedule_poll(struct ibm_ocp_mal *mal)
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{
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if (likely(napi_schedule_prep(&mal->napi))) {
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MAL_DBG2("%d: schedule_poll" NL, mal->def->index);
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mal_disable_eob_irq(mal);
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__napi_schedule(&mal->napi);
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} else
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MAL_DBG2("%d: already in poll" NL, mal->def->index);
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}
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static irqreturn_t mal_txeob(int irq, void *dev_instance)
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{
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struct ibm_ocp_mal *mal = dev_instance;
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u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
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MAL_DBG2("%d: txeob %08x" NL, mal->def->index, r);
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mal_schedule_poll(mal);
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set_mal_dcrn(mal, MAL_TXEOBISR, r);
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return IRQ_HANDLED;
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}
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static irqreturn_t mal_rxeob(int irq, void *dev_instance)
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{
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struct ibm_ocp_mal *mal = dev_instance;
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u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
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MAL_DBG2("%d: rxeob %08x" NL, mal->def->index, r);
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mal_schedule_poll(mal);
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set_mal_dcrn(mal, MAL_RXEOBISR, r);
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return IRQ_HANDLED;
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}
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static irqreturn_t mal_txde(int irq, void *dev_instance)
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{
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struct ibm_ocp_mal *mal = dev_instance;
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u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
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set_mal_dcrn(mal, MAL_TXDEIR, deir);
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MAL_DBG("%d: txde %08x" NL, mal->def->index, deir);
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if (net_ratelimit())
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printk(KERN_ERR
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"mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
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mal->def->index, deir);
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return IRQ_HANDLED;
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}
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static irqreturn_t mal_rxde(int irq, void *dev_instance)
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{
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struct ibm_ocp_mal *mal = dev_instance;
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struct list_head *l;
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u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
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MAL_DBG("%d: rxde %08x" NL, mal->def->index, deir);
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list_for_each(l, &mal->list) {
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struct mal_commac *mc = list_entry(l, struct mal_commac, list);
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if (deir & mc->rx_chan_mask) {
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mc->rx_stopped = 1;
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mc->ops->rxde(mc->dev);
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}
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}
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mal_schedule_poll(mal);
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set_mal_dcrn(mal, MAL_RXDEIR, deir);
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return IRQ_HANDLED;
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}
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static int mal_poll(struct napi_struct *napi, int budget)
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{
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struct ibm_ocp_mal *mal = container_of(napi, struct ibm_ocp_mal, napi);
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struct list_head *l;
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int received = 0;
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MAL_DBG2("%d: poll(%d) %d ->" NL, mal->def->index, *budget,
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rx_work_limit);
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again:
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/* Process TX skbs */
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list_for_each(l, &mal->poll_list) {
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struct mal_commac *mc =
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list_entry(l, struct mal_commac, poll_list);
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mc->ops->poll_tx(mc->dev);
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}
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/* Process RX skbs.
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* We _might_ need something more smart here to enforce polling fairness.
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*/
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list_for_each(l, &mal->poll_list) {
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struct mal_commac *mc =
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list_entry(l, struct mal_commac, poll_list);
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int n = mc->ops->poll_rx(mc->dev, budget);
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if (n) {
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received += n;
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budget -= n;
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if (budget <= 0)
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goto more_work; // XXX What if this is the last one ?
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}
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}
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/* We need to disable IRQs to protect from RXDE IRQ here */
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local_irq_disable();
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__napi_complete(napi);
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mal_enable_eob_irq(mal);
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local_irq_enable();
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/* Check for "rotting" packet(s) */
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list_for_each(l, &mal->poll_list) {
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struct mal_commac *mc =
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list_entry(l, struct mal_commac, poll_list);
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if (unlikely(mc->ops->peek_rx(mc->dev) || mc->rx_stopped)) {
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MAL_DBG2("%d: rotting packet" NL, mal->def->index);
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if (napi_reschedule(napi))
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mal_disable_eob_irq(mal);
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else
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MAL_DBG2("%d: already in poll list" NL,
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mal->def->index);
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if (budget > 0)
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goto again;
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else
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goto more_work;
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}
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mc->ops->poll_tx(mc->dev);
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}
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more_work:
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MAL_DBG2("%d: poll() %d <- %d" NL, mal->def->index, budget, received);
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return received;
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}
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static void mal_reset(struct ibm_ocp_mal *mal)
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{
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int n = 10;
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MAL_DBG("%d: reset" NL, mal->def->index);
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set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
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/* Wait for reset to complete (1 system clock) */
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while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
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--n;
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if (unlikely(!n))
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printk(KERN_ERR "mal%d: reset timeout\n", mal->def->index);
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}
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int mal_get_regs_len(struct ibm_ocp_mal *mal)
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{
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return sizeof(struct emac_ethtool_regs_subhdr) +
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sizeof(struct ibm_mal_regs);
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}
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void *mal_dump_regs(struct ibm_ocp_mal *mal, void *buf)
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{
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struct emac_ethtool_regs_subhdr *hdr = buf;
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struct ibm_mal_regs *regs = (struct ibm_mal_regs *)(hdr + 1);
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struct ocp_func_mal_data *maldata = mal->def->additions;
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int i;
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hdr->version = MAL_VERSION;
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hdr->index = mal->def->index;
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regs->tx_count = maldata->num_tx_chans;
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regs->rx_count = maldata->num_rx_chans;
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regs->cfg = get_mal_dcrn(mal, MAL_CFG);
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regs->esr = get_mal_dcrn(mal, MAL_ESR);
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regs->ier = get_mal_dcrn(mal, MAL_IER);
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regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
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regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
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regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
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regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
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regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
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regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
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regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
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regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
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for (i = 0; i < regs->tx_count; ++i)
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regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
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for (i = 0; i < regs->rx_count; ++i) {
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regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
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regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
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}
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return regs + 1;
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}
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static int __init mal_probe(struct ocp_device *ocpdev)
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{
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struct ibm_ocp_mal *mal;
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struct ocp_func_mal_data *maldata;
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int err = 0, i, bd_size;
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MAL_DBG("%d: probe" NL, ocpdev->def->index);
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maldata = ocpdev->def->additions;
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if (maldata == NULL) {
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printk(KERN_ERR "mal%d: missing additional data!\n",
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ocpdev->def->index);
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return -ENODEV;
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}
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mal = kzalloc(sizeof(struct ibm_ocp_mal), GFP_KERNEL);
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if (!mal) {
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printk(KERN_ERR
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"mal%d: out of memory allocating MAL structure!\n",
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ocpdev->def->index);
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return -ENOMEM;
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}
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/* XXX This only works for native dcr for now */
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mal->dcrhost = dcr_map(NULL, maldata->dcr_base, 0);
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mal->def = ocpdev->def;
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INIT_LIST_HEAD(&mal->poll_list);
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mal->napi.weight = CONFIG_IBM_EMAC_POLL_WEIGHT;
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mal->napi.poll = mal_poll;
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INIT_LIST_HEAD(&mal->list);
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/* Load power-on reset defaults */
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mal_reset(mal);
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/* Set the MAL configuration register */
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set_mal_dcrn(mal, MAL_CFG, MAL_CFG_DEFAULT | MAL_CFG_PLBB |
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MAL_CFG_OPBBL | MAL_CFG_LEA);
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mal_enable_eob_irq(mal);
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/* Allocate space for BD rings */
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BUG_ON(maldata->num_tx_chans <= 0 || maldata->num_tx_chans > 32);
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BUG_ON(maldata->num_rx_chans <= 0 || maldata->num_rx_chans > 32);
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bd_size = sizeof(struct mal_descriptor) *
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(NUM_TX_BUFF * maldata->num_tx_chans +
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NUM_RX_BUFF * maldata->num_rx_chans);
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mal->bd_virt =
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dma_alloc_coherent(&ocpdev->dev, bd_size, &mal->bd_dma, GFP_KERNEL);
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if (!mal->bd_virt) {
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printk(KERN_ERR
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"mal%d: out of memory allocating RX/TX descriptors!\n",
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mal->def->index);
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err = -ENOMEM;
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goto fail;
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}
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memset(mal->bd_virt, 0, bd_size);
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for (i = 0; i < maldata->num_tx_chans; ++i)
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set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
|
|
sizeof(struct mal_descriptor) *
|
|
mal_tx_bd_offset(mal, i));
|
|
|
|
for (i = 0; i < maldata->num_rx_chans; ++i)
|
|
set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
|
|
sizeof(struct mal_descriptor) *
|
|
mal_rx_bd_offset(mal, i));
|
|
|
|
err = request_irq(maldata->serr_irq, mal_serr, 0, "MAL SERR", mal);
|
|
if (err)
|
|
goto fail2;
|
|
err = request_irq(maldata->txde_irq, mal_txde, 0, "MAL TX DE", mal);
|
|
if (err)
|
|
goto fail3;
|
|
err = request_irq(maldata->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
|
|
if (err)
|
|
goto fail4;
|
|
err = request_irq(maldata->rxde_irq, mal_rxde, 0, "MAL RX DE", mal);
|
|
if (err)
|
|
goto fail5;
|
|
err = request_irq(maldata->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
|
|
if (err)
|
|
goto fail6;
|
|
|
|
/* Enable all MAL SERR interrupt sources */
|
|
set_mal_dcrn(mal, MAL_IER, MAL_IER_EVENTS);
|
|
|
|
/* Advertise this instance to the rest of the world */
|
|
ocp_set_drvdata(ocpdev, mal);
|
|
|
|
mal_dbg_register(mal->def->index, mal);
|
|
|
|
printk(KERN_INFO "mal%d: initialized, %d TX channels, %d RX channels\n",
|
|
mal->def->index, maldata->num_tx_chans, maldata->num_rx_chans);
|
|
return 0;
|
|
|
|
fail6:
|
|
free_irq(maldata->rxde_irq, mal);
|
|
fail5:
|
|
free_irq(maldata->txeob_irq, mal);
|
|
fail4:
|
|
free_irq(maldata->txde_irq, mal);
|
|
fail3:
|
|
free_irq(maldata->serr_irq, mal);
|
|
fail2:
|
|
dma_free_coherent(&ocpdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
|
|
fail:
|
|
kfree(mal);
|
|
return err;
|
|
}
|
|
|
|
static void __exit mal_remove(struct ocp_device *ocpdev)
|
|
{
|
|
struct ibm_ocp_mal *mal = ocp_get_drvdata(ocpdev);
|
|
struct ocp_func_mal_data *maldata = mal->def->additions;
|
|
|
|
MAL_DBG("%d: remove" NL, mal->def->index);
|
|
|
|
/* Synchronize with scheduled polling */
|
|
napi_disable(&mal->napi);
|
|
|
|
if (!list_empty(&mal->list)) {
|
|
/* This is *very* bad */
|
|
printk(KERN_EMERG
|
|
"mal%d: commac list is not empty on remove!\n",
|
|
mal->def->index);
|
|
}
|
|
|
|
ocp_set_drvdata(ocpdev, NULL);
|
|
|
|
free_irq(maldata->serr_irq, mal);
|
|
free_irq(maldata->txde_irq, mal);
|
|
free_irq(maldata->txeob_irq, mal);
|
|
free_irq(maldata->rxde_irq, mal);
|
|
free_irq(maldata->rxeob_irq, mal);
|
|
|
|
mal_reset(mal);
|
|
|
|
mal_dbg_register(mal->def->index, NULL);
|
|
|
|
dma_free_coherent(&ocpdev->dev,
|
|
sizeof(struct mal_descriptor) *
|
|
(NUM_TX_BUFF * maldata->num_tx_chans +
|
|
NUM_RX_BUFF * maldata->num_rx_chans), mal->bd_virt,
|
|
mal->bd_dma);
|
|
|
|
kfree(mal);
|
|
}
|
|
|
|
/* Structure for a device driver */
|
|
static struct ocp_device_id mal_ids[] = {
|
|
{ .vendor = OCP_VENDOR_IBM, .function = OCP_FUNC_MAL },
|
|
{ .vendor = OCP_VENDOR_INVALID}
|
|
};
|
|
|
|
static struct ocp_driver mal_driver = {
|
|
.name = "mal",
|
|
.id_table = mal_ids,
|
|
|
|
.probe = mal_probe,
|
|
.remove = mal_remove,
|
|
};
|
|
|
|
int __init mal_init(void)
|
|
{
|
|
MAL_DBG(": init" NL);
|
|
return ocp_register_driver(&mal_driver);
|
|
}
|
|
|
|
void __exit mal_exit(void)
|
|
{
|
|
MAL_DBG(": exit" NL);
|
|
ocp_unregister_driver(&mal_driver);
|
|
}
|