9eba4a93ce
The CMASK RAM is for colorbuffer compression (used in conjunction with MSAA). Only one user (filp) can access it. The CMASK RAM access is managed in the same way as Hyper-Z, but there is a separate ioctl, because an app that uses MSAA does not necessarily have to use zbuffering. Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
404 lines
13 KiB
C
404 lines
13 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include "drmP.h"
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#include "drm_sarea.h"
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#include "radeon.h"
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#include "radeon_drm.h"
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#include <linux/vga_switcheroo.h>
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#include <linux/slab.h>
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int radeon_driver_unload_kms(struct drm_device *dev)
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{
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struct radeon_device *rdev = dev->dev_private;
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if (rdev == NULL)
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return 0;
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radeon_modeset_fini(rdev);
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radeon_device_fini(rdev);
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kfree(rdev);
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dev->dev_private = NULL;
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return 0;
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}
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int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
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{
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struct radeon_device *rdev;
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int r, acpi_status;
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rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
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if (rdev == NULL) {
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return -ENOMEM;
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}
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dev->dev_private = (void *)rdev;
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/* update BUS flag */
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if (drm_device_is_agp(dev)) {
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flags |= RADEON_IS_AGP;
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} else if (drm_device_is_pcie(dev)) {
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flags |= RADEON_IS_PCIE;
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} else {
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flags |= RADEON_IS_PCI;
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}
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/* radeon_device_init should report only fatal error
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* like memory allocation failure or iomapping failure,
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* or memory manager initialization failure, it must
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* properly initialize the GPU MC controller and permit
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* VRAM allocation
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*/
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r = radeon_device_init(rdev, dev, dev->pdev, flags);
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if (r) {
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dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
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goto out;
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}
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/* Call ACPI methods */
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acpi_status = radeon_acpi_init(rdev);
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if (acpi_status)
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dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
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/* Again modeset_init should fail only on fatal error
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* otherwise it should provide enough functionalities
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* for shadowfb to run
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*/
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r = radeon_modeset_init(rdev);
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if (r)
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dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
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out:
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if (r)
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radeon_driver_unload_kms(dev);
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return r;
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}
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static void radeon_set_filp_rights(struct drm_device *dev,
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struct drm_file **owner,
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struct drm_file *applier,
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uint32_t *value)
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{
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mutex_lock(&dev->struct_mutex);
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if (*value == 1) {
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/* wants rights */
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if (!*owner)
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*owner = applier;
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} else if (*value == 0) {
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/* revokes rights */
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if (*owner == applier)
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*owner = NULL;
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}
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*value = *owner == applier ? 1 : 0;
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mutex_unlock(&dev->struct_mutex);
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}
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/*
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* Userspace get information ioctl
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*/
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int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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{
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struct radeon_device *rdev = dev->dev_private;
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struct drm_radeon_info *info;
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struct radeon_mode_info *minfo = &rdev->mode_info;
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uint32_t *value_ptr;
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uint32_t value;
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struct drm_crtc *crtc;
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int i, found;
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info = data;
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value_ptr = (uint32_t *)((unsigned long)info->value);
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if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
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return -EFAULT;
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switch (info->request) {
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case RADEON_INFO_DEVICE_ID:
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value = dev->pci_device;
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break;
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case RADEON_INFO_NUM_GB_PIPES:
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value = rdev->num_gb_pipes;
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break;
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case RADEON_INFO_NUM_Z_PIPES:
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value = rdev->num_z_pipes;
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break;
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case RADEON_INFO_ACCEL_WORKING:
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/* xf86-video-ati 6.13.0 relies on this being false for evergreen */
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if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
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value = false;
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else
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value = rdev->accel_working;
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break;
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case RADEON_INFO_CRTC_FROM_ID:
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for (i = 0, found = 0; i < rdev->num_crtc; i++) {
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crtc = (struct drm_crtc *)minfo->crtcs[i];
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if (crtc && crtc->base.id == value) {
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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value = radeon_crtc->crtc_id;
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found = 1;
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break;
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}
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}
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if (!found) {
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DRM_DEBUG_KMS("unknown crtc id %d\n", value);
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return -EINVAL;
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}
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break;
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case RADEON_INFO_ACCEL_WORKING2:
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value = rdev->accel_working;
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break;
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case RADEON_INFO_TILING_CONFIG:
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if (rdev->family >= CHIP_CEDAR)
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value = rdev->config.evergreen.tile_config;
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else if (rdev->family >= CHIP_RV770)
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value = rdev->config.rv770.tile_config;
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else if (rdev->family >= CHIP_R600)
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value = rdev->config.r600.tile_config;
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else {
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DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
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return -EINVAL;
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}
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break;
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case RADEON_INFO_WANT_HYPERZ:
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/* The "value" here is both an input and output parameter.
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* If the input value is 1, filp requests hyper-z access.
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* If the input value is 0, filp revokes its hyper-z access.
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*
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* When returning, the value is 1 if filp owns hyper-z access,
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* 0 otherwise. */
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if (value >= 2) {
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DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
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return -EINVAL;
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}
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radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
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break;
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case RADEON_INFO_WANT_CMASK:
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/* The same logic as Hyper-Z. */
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if (value >= 2) {
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DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
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return -EINVAL;
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}
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radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
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break;
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default:
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DRM_DEBUG_KMS("Invalid request %d\n", info->request);
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return -EINVAL;
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}
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if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
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DRM_ERROR("copy_to_user\n");
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return -EFAULT;
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}
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return 0;
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}
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/*
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* Outdated mess for old drm with Xorg being in charge (void function now).
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*/
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int radeon_driver_firstopen_kms(struct drm_device *dev)
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{
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return 0;
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}
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void radeon_driver_lastclose_kms(struct drm_device *dev)
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{
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vga_switcheroo_process_delayed_switch();
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}
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int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
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{
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return 0;
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}
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void radeon_driver_postclose_kms(struct drm_device *dev,
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struct drm_file *file_priv)
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{
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}
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void radeon_driver_preclose_kms(struct drm_device *dev,
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struct drm_file *file_priv)
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{
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struct radeon_device *rdev = dev->dev_private;
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if (rdev->hyperz_filp == file_priv)
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rdev->hyperz_filp = NULL;
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}
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/*
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* VBlank related functions.
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*/
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u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
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{
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struct radeon_device *rdev = dev->dev_private;
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if (crtc < 0 || crtc >= rdev->num_crtc) {
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DRM_ERROR("Invalid crtc %d\n", crtc);
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return -EINVAL;
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}
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return radeon_get_vblank_counter(rdev, crtc);
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}
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int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
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{
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struct radeon_device *rdev = dev->dev_private;
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if (crtc < 0 || crtc >= rdev->num_crtc) {
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DRM_ERROR("Invalid crtc %d\n", crtc);
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return -EINVAL;
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}
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rdev->irq.crtc_vblank_int[crtc] = true;
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return radeon_irq_set(rdev);
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}
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void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
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{
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struct radeon_device *rdev = dev->dev_private;
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if (crtc < 0 || crtc >= rdev->num_crtc) {
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DRM_ERROR("Invalid crtc %d\n", crtc);
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return;
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}
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rdev->irq.crtc_vblank_int[crtc] = false;
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radeon_irq_set(rdev);
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}
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int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
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int *max_error,
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struct timeval *vblank_time,
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unsigned flags)
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{
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struct drm_crtc *drmcrtc;
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struct radeon_device *rdev = dev->dev_private;
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if (crtc < 0 || crtc >= dev->num_crtcs) {
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DRM_ERROR("Invalid crtc %d\n", crtc);
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return -EINVAL;
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}
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/* Get associated drm_crtc: */
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drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
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/* Helper routine in DRM core does all the work: */
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return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
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vblank_time, flags,
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drmcrtc);
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}
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/*
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* IOCTL.
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*/
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int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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/* Not valid in KMS. */
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return -EINVAL;
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}
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#define KMS_INVALID_IOCTL(name) \
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int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
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{ \
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DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
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return -EINVAL; \
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}
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/*
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* All these ioctls are invalid in kms world.
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*/
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KMS_INVALID_IOCTL(radeon_cp_init_kms)
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KMS_INVALID_IOCTL(radeon_cp_start_kms)
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KMS_INVALID_IOCTL(radeon_cp_stop_kms)
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KMS_INVALID_IOCTL(radeon_cp_reset_kms)
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KMS_INVALID_IOCTL(radeon_cp_idle_kms)
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KMS_INVALID_IOCTL(radeon_cp_resume_kms)
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KMS_INVALID_IOCTL(radeon_engine_reset_kms)
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KMS_INVALID_IOCTL(radeon_fullscreen_kms)
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KMS_INVALID_IOCTL(radeon_cp_swap_kms)
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KMS_INVALID_IOCTL(radeon_cp_clear_kms)
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KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
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KMS_INVALID_IOCTL(radeon_cp_indices_kms)
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KMS_INVALID_IOCTL(radeon_cp_texture_kms)
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KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
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KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
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KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
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KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
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KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
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KMS_INVALID_IOCTL(radeon_cp_flip_kms)
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KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
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KMS_INVALID_IOCTL(radeon_mem_free_kms)
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KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
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KMS_INVALID_IOCTL(radeon_irq_emit_kms)
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KMS_INVALID_IOCTL(radeon_irq_wait_kms)
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KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
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KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
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KMS_INVALID_IOCTL(radeon_surface_free_kms)
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struct drm_ioctl_desc radeon_ioctls_kms[] = {
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DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
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/* KMS */
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DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
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};
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int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);
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