d1bef4ed5f
This patch-queue improves the generic IRQ layer to be truly generic, by adding various abstractions and features to it, without impacting existing functionality. While the queue can be best described as "fix and improve everything in the generic IRQ layer that we could think of", and thus it consists of many smaller features and lots of cleanups, the one feature that stands out most is the new 'irq chip' abstraction. The irq-chip abstraction is about describing and coding and IRQ controller driver by mapping its raw hardware capabilities [and quirks, if needed] in a straightforward way, without having to think about "IRQ flow" (level/edge/etc.) type of details. This stands in contrast with the current 'irq-type' model of genirq architectures, which 'mixes' raw hardware capabilities with 'flow' details. The patchset supports both types of irq controller designs at once, and converts i386 and x86_64 to the new irq-chip design. As a bonus side-effect of the irq-chip approach, chained interrupt controllers (master/slave PIC constructs, etc.) are now supported by design as well. The end result of this patchset intends to be simpler architecture-level code and more consolidation between architectures. We reused many bits of code and many concepts from Russell King's ARM IRQ layer, the merging of which was one of the motivations for this patchset. This patch: rename desc->handler to desc->chip. Originally i did not want to do this, because it's a big patch. But having both "desc->handler", "desc->handle_irq" and "action->handler" caused a large degree of confusion and made the code appear alot less clean than it truly is. I have also attempted a dual approach as well by introducing a desc->chip alias - but that just wasnt robust enough and broke frequently. So lets get over with this quickly. The conversion was done automatically via scripts and converts all the code in the kernel. This renaming patch is the first one amongst the patches, so that the remaining patches can stay flexible and can be merged and split up without having some big monolithic patch act as a merge barrier. [akpm@osdl.org: build fix] [akpm@osdl.org: another build fix] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
210 lines
5 KiB
C
210 lines
5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1992 Linus Torvalds
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* Copyright (C) 1994 - 2000 Ralf Baechle
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <asm/i8259.h>
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#include <asm/io.h>
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#include <asm/sni.h>
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DEFINE_SPINLOCK(pciasic_lock);
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static void enable_pciasic_irq(unsigned int irq)
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{
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unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
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unsigned long flags;
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spin_lock_irqsave(&pciasic_lock, flags);
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*(volatile u8 *) PCIMT_IRQSEL |= mask;
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spin_unlock_irqrestore(&pciasic_lock, flags);
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}
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static unsigned int startup_pciasic_irq(unsigned int irq)
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{
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enable_pciasic_irq(irq);
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return 0; /* never anything pending */
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}
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#define shutdown_pciasic_irq disable_pciasic_irq
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void disable_pciasic_irq(unsigned int irq)
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{
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unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
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unsigned long flags;
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spin_lock_irqsave(&pciasic_lock, flags);
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*(volatile u8 *) PCIMT_IRQSEL &= mask;
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spin_unlock_irqrestore(&pciasic_lock, flags);
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}
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#define mask_and_ack_pciasic_irq disable_pciasic_irq
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static void end_pciasic_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_pciasic_irq(irq);
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}
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static struct hw_interrupt_type pciasic_irq_type = {
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.typename = "ASIC-PCI",
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.startup = startup_pciasic_irq,
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.shutdown = shutdown_pciasic_irq,
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.enable = enable_pciasic_irq,
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.disable = disable_pciasic_irq,
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.ack = mask_and_ack_pciasic_irq,
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.end = end_pciasic_irq,
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};
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/*
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* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
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* button interrupts. Later ...
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*/
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static void pciasic_hwint0(struct pt_regs *regs)
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{
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panic("Received int0 but no handler yet ...");
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}
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/* This interrupt was used for the com1 console on the first prototypes. */
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static void pciasic_hwint2(struct pt_regs *regs)
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{
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/* I think this shouldn't happen on production machines. */
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panic("hwint2 and no handler yet");
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}
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/* hwint5 is the r4k count / compare interrupt */
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static void pciasic_hwint5(struct pt_regs *regs)
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{
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panic("hwint5 and no handler yet");
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}
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static unsigned int ls1bit8(unsigned int x)
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{
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int b = 7, s;
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s = 4; if ((x & 0x0f) == 0) s = 0; b -= s; x <<= s;
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s = 2; if ((x & 0x30) == 0) s = 0; b -= s; x <<= s;
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s = 1; if ((x & 0x40) == 0) s = 0; b -= s;
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return b;
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}
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/*
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* hwint 1 deals with EISA and SCSI interrupts,
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*
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* The EISA_INT bit in CSITPEND is high active, all others are low active.
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*/
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static void pciasic_hwint1(struct pt_regs *regs)
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{
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u8 pend = *(volatile char *)PCIMT_CSITPEND;
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unsigned long flags;
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if (pend & IT_EISA) {
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int irq;
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/*
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* Note: ASIC PCI's builtin interrupt achknowledge feature is
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* broken. Using it may result in loss of some or all i8259
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* interupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
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*/
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irq = i8259_irq();
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if (unlikely(irq < 0))
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return;
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do_IRQ(irq, regs);
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}
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if (!(pend & IT_SCSI)) {
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flags = read_c0_status();
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clear_c0_status(ST0_IM);
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do_IRQ(PCIMT_IRQ_SCSI, regs);
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write_c0_status(flags);
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}
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}
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/*
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* hwint 3 should deal with the PCI A - D interrupts,
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*/
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static void pciasic_hwint3(struct pt_regs *regs)
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{
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u8 pend = *(volatile char *)PCIMT_CSITPEND;
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int irq;
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pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
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clear_c0_status(IE_IRQ3);
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irq = PCIMT_IRQ_INT2 + ls1bit8(pend);
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do_IRQ(irq, regs);
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set_c0_status(IE_IRQ3);
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}
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/*
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* hwint 4 is used for only the onboard PCnet 32.
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*/
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static void pciasic_hwint4(struct pt_regs *regs)
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{
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clear_c0_status(IE_IRQ4);
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do_IRQ(PCIMT_IRQ_ETHERNET, regs);
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set_c0_status(IE_IRQ4);
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}
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asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
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{
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unsigned int pending = read_c0_status() & read_c0_cause();
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static unsigned char led_cache;
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*(volatile unsigned char *) PCIMT_CSLED = ++led_cache;
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if (pending & 0x0800)
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pciasic_hwint1(regs);
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else if (pending & 0x4000)
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pciasic_hwint4(regs);
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else if (pending & 0x2000)
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pciasic_hwint3(regs);
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else if (pending & 0x1000)
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pciasic_hwint2(regs);
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else if (pending & 0x8000)
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pciasic_hwint5(regs);
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else if (pending & 0x0400)
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pciasic_hwint0(regs);
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}
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void __init init_pciasic(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&pciasic_lock, flags);
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* (volatile u8 *) PCIMT_IRQSEL =
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IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD;
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spin_unlock_irqrestore(&pciasic_lock, flags);
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}
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/*
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* On systems with i8259-style interrupt controllers we assume for
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* driver compatibility reasons interrupts 0 - 15 to be the i8295
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* interrupts even if the hardware uses a different interrupt numbering.
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*/
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void __init arch_init_irq(void)
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{
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int i;
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init_i8259_irqs(); /* Integrated i8259 */
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init_pciasic();
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/* Actually we've got more interrupts to handle ... */
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for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &pciasic_irq_type;
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}
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change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
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}
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