Atsushi Nemoto d10e025f0e MIPS: TXx9: Cache fixup ... TX39/TX49 can enable/disable I/D cache at runtime. Add kernel options to control them. This is useful to debug some cache-related issues, such as aliasing or I/D coherency. Also enable CWF bit for TX49 SoCs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2008-10-11 16:18:42 +01:00
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irq.c	[MIPS] TXx9: Random cleanup	2008-07-30 21:54:40 +01:00
Makefile	[MIPS] kgdb: Remove existing implementation	2008-07-30 21:54:42 +01:00
prom.c	MIPS: TXx9: Improve handling of built-in and command-line args	2008-10-11 16:18:41 +01:00
setup.c	MIPS: TXx9: Cache fixup	2008-10-11 16:18:42 +01:00