446 lines
12 KiB
C
446 lines
12 KiB
C
/*
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* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
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* Due to massive hardware bugs, UltraDMA is only supported
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* on the 646U2 and not on the 646U.
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*
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* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
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* Copyright (C) 1998 David S. Miller (davem@redhat.com)
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*
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* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
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* Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#define DRV_NAME "cmd64x"
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/*
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* CMD64x specific registers definition.
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*/
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#define CFR 0x50
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#define CFR_INTR_CH0 0x04
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#define CMDTIM 0x52
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#define ARTTIM0 0x53
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#define DRWTIM0 0x54
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#define ARTTIM1 0x55
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#define DRWTIM1 0x56
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#define ARTTIM23 0x57
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#define ARTTIM23_DIS_RA2 0x04
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#define ARTTIM23_DIS_RA3 0x08
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#define ARTTIM23_INTR_CH1 0x10
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#define DRWTIM2 0x58
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#define BRST 0x59
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#define DRWTIM3 0x5b
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#define BMIDECR0 0x70
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#define MRDMODE 0x71
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#define MRDMODE_INTR_CH0 0x04
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#define MRDMODE_INTR_CH1 0x08
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#define UDIDETCR0 0x73
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#define DTPR0 0x74
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#define BMIDECR1 0x78
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#define BMIDECSR 0x79
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#define UDIDETCR1 0x7B
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#define DTPR1 0x7C
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static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
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const unsigned long T = 1000000 / bus_speed;
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static const u8 recovery_values[] =
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{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
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static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
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static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
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static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
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struct ide_timing t;
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u8 arttim = 0;
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ide_timing_compute(drive, mode, &t, T, 0);
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/*
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* In case we've got too long recovery phase, try to lengthen
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* the active phase
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*/
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if (t.recover > 16) {
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t.active += t.recover - 16;
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t.recover = 16;
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}
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if (t.active > 16) /* shouldn't actually happen... */
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t.active = 16;
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/*
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* Convert values to internal chipset representation
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*/
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t.recover = recovery_values[t.recover];
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t.active &= 0x0f;
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/* Program the active/recovery counts into the DRWTIM register */
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pci_write_config_byte(dev, drwtim_regs[drive->dn],
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(t.active << 4) | t.recover);
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if (mode >= XFER_SW_DMA_0)
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return;
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/*
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* The primary channel has individual address setup timing registers
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* for each drive and the hardware selects the slowest timing itself.
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* The secondary channel has one common register and we have to select
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* the slowest address setup timing ourselves.
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*/
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if (hwif->channel) {
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ide_drive_t *pair = ide_get_pair_dev(drive);
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ide_set_drivedata(drive, (void *)(unsigned long)t.setup);
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if (pair)
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t.setup = max_t(u8, t.setup,
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(unsigned long)ide_get_drivedata(pair));
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}
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if (t.setup > 5) /* shouldn't actually happen... */
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t.setup = 5;
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/*
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* Program the address setup clocks into the ARTTIM registers.
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* Avoid clearing the secondary channel's interrupt bit.
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*/
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(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
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if (hwif->channel)
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arttim &= ~ARTTIM23_INTR_CH1;
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arttim &= ~0xc0;
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arttim |= setup_values[t.setup];
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(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
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}
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/*
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* Attempts to set drive's PIO mode.
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* Special cases are 8: prefetch off, 9: prefetch on (both never worked)
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*/
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static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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const u8 pio = drive->pio_mode - XFER_PIO_0;
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/*
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* Filter out the prefetch control values
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* to prevent PIO5 from being programmed
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*/
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if (pio == 8 || pio == 9)
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return;
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cmd64x_program_timings(drive, XFER_PIO_0 + pio);
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}
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static void cmd64x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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u8 unit = drive->dn & 0x01;
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u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
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const u8 speed = drive->dma_mode;
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pci_read_config_byte(dev, pciU, ®U);
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regU &= ~(unit ? 0xCA : 0x35);
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switch(speed) {
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case XFER_UDMA_5:
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regU |= unit ? 0x0A : 0x05;
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break;
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case XFER_UDMA_4:
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regU |= unit ? 0x4A : 0x15;
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break;
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case XFER_UDMA_3:
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regU |= unit ? 0x8A : 0x25;
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break;
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case XFER_UDMA_2:
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regU |= unit ? 0x42 : 0x11;
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break;
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case XFER_UDMA_1:
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regU |= unit ? 0x82 : 0x21;
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break;
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case XFER_UDMA_0:
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regU |= unit ? 0xC2 : 0x31;
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break;
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case XFER_MW_DMA_2:
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case XFER_MW_DMA_1:
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case XFER_MW_DMA_0:
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cmd64x_program_timings(drive, speed);
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break;
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}
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pci_write_config_byte(dev, pciU, regU);
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}
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static void cmd648_clear_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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unsigned long base = pci_resource_start(dev, 4);
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u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
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MRDMODE_INTR_CH0;
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u8 mrdmode = inb(base + 1);
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/* clear the interrupt bit */
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outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
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base + 1);
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}
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static void cmd64x_clear_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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int irq_reg = hwif->channel ? ARTTIM23 : CFR;
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u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
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CFR_INTR_CH0;
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u8 irq_stat = 0;
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(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
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/* clear the interrupt bit */
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(void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
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}
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static int cmd648_test_irq(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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unsigned long base = pci_resource_start(dev, 4);
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u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
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MRDMODE_INTR_CH0;
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u8 mrdmode = inb(base + 1);
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pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
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hwif->name, mrdmode, irq_mask);
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return (mrdmode & irq_mask) ? 1 : 0;
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}
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static int cmd64x_test_irq(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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int irq_reg = hwif->channel ? ARTTIM23 : CFR;
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u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
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CFR_INTR_CH0;
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u8 irq_stat = 0;
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(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
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pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
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hwif->name, irq_stat, irq_mask);
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return (irq_stat & irq_mask) ? 1 : 0;
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}
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/*
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* ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
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* event order for DMA transfers.
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*/
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static int cmd646_1_dma_end(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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u8 dma_stat = 0, dma_cmd = 0;
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/* get DMA status */
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dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
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/* read DMA command state */
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dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
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/* stop DMA */
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outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
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/* clear the INTR & ERROR bits */
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outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
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/* verify good DMA status */
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return (dma_stat & 7) != 4;
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}
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static int init_chipset_cmd64x(struct pci_dev *dev)
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{
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u8 mrdmode = 0;
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/* Set a good latency timer and cache line size value. */
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(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
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/* FIXME: pci_set_master() to ensure a good latency timer value */
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/*
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* Enable interrupts, select MEMORY READ LINE for reads.
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*
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* NOTE: although not mentioned in the PCI0646U specs,
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* bits 0-1 are write only and won't be read back as
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* set or not -- PCI0646U2 specs clarify this point.
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*/
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(void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
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mrdmode &= ~0x30;
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(void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
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return 0;
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}
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static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
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switch (dev->device) {
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case PCI_DEVICE_ID_CMD_648:
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case PCI_DEVICE_ID_CMD_649:
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pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
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return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
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default:
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return ATA_CBL_PATA40;
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}
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}
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static const struct ide_port_ops cmd64x_port_ops = {
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.set_pio_mode = cmd64x_set_pio_mode,
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.set_dma_mode = cmd64x_set_dma_mode,
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.clear_irq = cmd64x_clear_irq,
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.test_irq = cmd64x_test_irq,
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.cable_detect = cmd64x_cable_detect,
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};
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static const struct ide_port_ops cmd648_port_ops = {
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.set_pio_mode = cmd64x_set_pio_mode,
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.set_dma_mode = cmd64x_set_dma_mode,
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.clear_irq = cmd648_clear_irq,
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.test_irq = cmd648_test_irq,
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.cable_detect = cmd64x_cable_detect,
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};
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static const struct ide_dma_ops cmd646_rev1_dma_ops = {
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.dma_host_set = ide_dma_host_set,
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.dma_setup = ide_dma_setup,
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.dma_start = ide_dma_start,
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.dma_end = cmd646_1_dma_end,
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.dma_test_irq = ide_dma_test_irq,
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.dma_lost_irq = ide_dma_lost_irq,
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.dma_timer_expiry = ide_dma_sff_timer_expiry,
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.dma_sff_read_status = ide_dma_sff_read_status,
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};
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static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
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{ /* 0: CMD643 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_cmd64x,
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.enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
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.port_ops = &cmd64x_port_ops,
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.host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
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IDE_HFLAG_ABUSE_PREFETCH |
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IDE_HFLAG_SERIALIZE,
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.pio_mask = ATA_PIO5,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = 0x00, /* no udma */
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},
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{ /* 1: CMD646 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_cmd64x,
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.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
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.port_ops = &cmd648_port_ops,
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.host_flags = IDE_HFLAG_ABUSE_PREFETCH |
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IDE_HFLAG_SERIALIZE,
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.pio_mask = ATA_PIO5,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA2,
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},
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{ /* 2: CMD648 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_cmd64x,
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.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
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.port_ops = &cmd648_port_ops,
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.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
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.pio_mask = ATA_PIO5,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA4,
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},
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{ /* 3: CMD649 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_cmd64x,
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.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
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.port_ops = &cmd648_port_ops,
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.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
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.pio_mask = ATA_PIO5,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA5,
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}
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};
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static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct ide_port_info d;
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u8 idx = id->driver_data;
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d = cmd64x_chipsets[idx];
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if (idx == 1) {
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/*
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* UltraDMA only supported on PCI646U and PCI646U2, which
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* correspond to revisions 0x03, 0x05 and 0x07 respectively.
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* Actually, although the CMD tech support people won't
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* tell me the details, the 0x03 revision cannot support
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* UDMA correctly without hardware modifications, and even
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* then it only works with Quantum disks due to some
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* hold time assumptions in the 646U part which are fixed
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* in the 646U2.
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*
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* So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
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*/
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if (dev->revision < 5) {
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d.udma_mask = 0x00;
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/*
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* The original PCI0646 didn't have the primary
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* channel enable bit, it appeared starting with
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* PCI0646U (i.e. revision ID 3).
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*/
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if (dev->revision < 3) {
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d.enablebits[0].reg = 0;
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d.port_ops = &cmd64x_port_ops;
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if (dev->revision == 1)
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d.dma_ops = &cmd646_rev1_dma_ops;
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}
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}
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}
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return ide_pci_init_one(dev, &d, NULL);
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}
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static const struct pci_device_id cmd64x_pci_tbl[] = {
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{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
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{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
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{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
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{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
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static struct pci_driver cmd64x_pci_driver = {
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.name = "CMD64x_IDE",
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.id_table = cmd64x_pci_tbl,
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.probe = cmd64x_init_one,
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.remove = ide_pci_remove,
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.suspend = ide_pci_suspend,
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.resume = ide_pci_resume,
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};
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static int __init cmd64x_ide_init(void)
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{
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return ide_pci_register_driver(&cmd64x_pci_driver);
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}
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static void __exit cmd64x_ide_exit(void)
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{
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pci_unregister_driver(&cmd64x_pci_driver);
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}
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module_init(cmd64x_ide_init);
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module_exit(cmd64x_ide_exit);
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MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
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MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
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MODULE_LICENSE("GPL");
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