cd4a05f9df
This allows us to have more mapping functions for more than one i.MX architecture in the kernel. As this is the earliest board specific hook we have, also use it to set the cpu type. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
302 lines
7 KiB
C
302 lines
7 KiB
C
/*
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* Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
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* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/plat-ram.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/i2c/at24.h>
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#include <asm/mach/arch.h>
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#include <asm/mach-types.h>
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#include <mach/common.h>
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#include <mach/hardware.h>
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#include <mach/iomux.h>
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#ifdef CONFIG_I2C_IMX
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#include <mach/i2c.h>
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#endif
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#include <asm/mach/time.h>
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#include <mach/imx-uart.h>
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#include <mach/board-pcm038.h>
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#include <mach/mxc_nand.h>
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#include "devices.h"
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/*
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* Phytec's PCM038 comes with 2MiB battery buffered SRAM,
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* 16 bit width
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*/
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static struct platdata_mtd_ram pcm038_sram_data = {
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.bankwidth = 2,
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};
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static struct resource pcm038_sram_resource = {
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.start = CS1_BASE_ADDR,
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.end = CS1_BASE_ADDR + 512 * 1024 - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device pcm038_sram_mtd_device = {
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.name = "mtd-ram",
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.id = 0,
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.dev = {
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.platform_data = &pcm038_sram_data,
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},
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.num_resources = 1,
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.resource = &pcm038_sram_resource,
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};
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/*
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* Phytec's phyCORE-i.MX27 comes with 32MiB flash,
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* 16 bit width
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*/
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static struct physmap_flash_data pcm038_flash_data = {
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.width = 2,
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};
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static struct resource pcm038_flash_resource = {
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.start = 0xc0000000,
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.end = 0xc1ffffff,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device pcm038_nor_mtd_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &pcm038_flash_data,
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},
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.num_resources = 1,
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.resource = &pcm038_flash_resource,
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};
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static int mxc_uart0_pins[] = {
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PE12_PF_UART1_TXD,
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PE13_PF_UART1_RXD,
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PE14_PF_UART1_CTS,
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PE15_PF_UART1_RTS
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};
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static int uart_mxc_port0_init(struct platform_device *pdev)
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{
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return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
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ARRAY_SIZE(mxc_uart0_pins), "UART0");
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}
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static int uart_mxc_port0_exit(struct platform_device *pdev)
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{
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mxc_gpio_release_multiple_pins(mxc_uart0_pins,
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ARRAY_SIZE(mxc_uart0_pins));
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return 0;
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}
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static int mxc_uart1_pins[] = {
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PE3_PF_UART2_CTS,
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PE4_PF_UART2_RTS,
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PE6_PF_UART2_TXD,
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PE7_PF_UART2_RXD
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};
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static int uart_mxc_port1_init(struct platform_device *pdev)
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{
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return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
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ARRAY_SIZE(mxc_uart1_pins), "UART1");
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}
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static int uart_mxc_port1_exit(struct platform_device *pdev)
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{
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mxc_gpio_release_multiple_pins(mxc_uart1_pins,
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ARRAY_SIZE(mxc_uart1_pins));
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return 0;
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}
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static int mxc_uart2_pins[] = { PE8_PF_UART3_TXD,
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PE9_PF_UART3_RXD,
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PE10_PF_UART3_CTS,
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PE11_PF_UART3_RTS };
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static int uart_mxc_port2_init(struct platform_device *pdev)
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{
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return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
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ARRAY_SIZE(mxc_uart2_pins), "UART2");
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}
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static int uart_mxc_port2_exit(struct platform_device *pdev)
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{
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mxc_gpio_release_multiple_pins(mxc_uart2_pins,
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ARRAY_SIZE(mxc_uart2_pins));
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return 0;
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}
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static struct imxuart_platform_data uart_pdata[] = {
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{
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.init = uart_mxc_port0_init,
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.exit = uart_mxc_port0_exit,
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.flags = IMXUART_HAVE_RTSCTS,
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}, {
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.init = uart_mxc_port1_init,
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.exit = uart_mxc_port1_exit,
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.flags = IMXUART_HAVE_RTSCTS,
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}, {
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.init = uart_mxc_port2_init,
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.exit = uart_mxc_port2_exit,
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.flags = IMXUART_HAVE_RTSCTS,
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},
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};
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static int mxc_fec_pins[] = {
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PD0_AIN_FEC_TXD0,
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PD1_AIN_FEC_TXD1,
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PD2_AIN_FEC_TXD2,
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PD3_AIN_FEC_TXD3,
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PD4_AOUT_FEC_RX_ER,
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PD5_AOUT_FEC_RXD1,
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PD6_AOUT_FEC_RXD2,
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PD7_AOUT_FEC_RXD3,
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PD8_AF_FEC_MDIO,
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PD9_AIN_FEC_MDC,
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PD10_AOUT_FEC_CRS,
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PD11_AOUT_FEC_TX_CLK,
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PD12_AOUT_FEC_RXD0,
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PD13_AOUT_FEC_RX_DV,
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PD14_AOUT_FEC_RX_CLK,
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PD15_AOUT_FEC_COL,
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PD16_AIN_FEC_TX_ER,
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PF23_AIN_FEC_TX_EN
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};
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static void gpio_fec_active(void)
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{
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mxc_gpio_setup_multiple_pins(mxc_fec_pins,
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ARRAY_SIZE(mxc_fec_pins), "FEC");
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}
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static struct mxc_nand_platform_data pcm038_nand_board_info = {
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.width = 1,
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.hw_ecc = 1,
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};
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static struct platform_device *platform_devices[] __initdata = {
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&pcm038_nor_mtd_device,
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&mxc_w1_master_device,
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&mxc_fec_device,
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&pcm038_sram_mtd_device,
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};
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/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
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* setup other stuffs to access the sram. */
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static void __init pcm038_init_sram(void)
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{
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__raw_writel(0x0000d843, CSCR_U(1));
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__raw_writel(0x22252521, CSCR_L(1));
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__raw_writel(0x22220a00, CSCR_A(1));
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}
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#ifdef CONFIG_I2C_IMX
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static int mxc_i2c1_pins[] = {
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PC5_PF_I2C2_SDA,
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PC6_PF_I2C2_SCL
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};
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static int pcm038_i2c_1_init(struct device *dev)
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{
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return mxc_gpio_setup_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins),
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"I2C1");
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}
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static void pcm038_i2c_1_exit(struct device *dev)
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{
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mxc_gpio_release_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins));
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}
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static struct imxi2c_platform_data pcm038_i2c_1_data = {
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.bitrate = 100000,
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.init = pcm038_i2c_1_init,
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.exit = pcm038_i2c_1_exit,
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};
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static struct at24_platform_data board_eeprom = {
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.byte_len = 4096,
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.page_size = 32,
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.flags = AT24_FLAG_ADDR16,
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};
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static struct i2c_board_info pcm038_i2c_devices[] = {
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[0] = {
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I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
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.platform_data = &board_eeprom,
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},
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[1] = {
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I2C_BOARD_INFO("rtc-pcf8563", 0x51),
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.type = "pcf8563"
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},
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[2] = {
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I2C_BOARD_INFO("lm75", 0x4a),
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.type = "lm75"
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}
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};
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#endif
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static void __init pcm038_init(void)
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{
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gpio_fec_active();
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pcm038_init_sram();
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mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
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mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
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mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
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mxc_gpio_mode(PE16_AF_OWIRE);
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mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);
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#ifdef CONFIG_I2C_IMX
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/* only the i2c master 1 is used on this CPU card */
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i2c_register_board_info(1, pcm038_i2c_devices,
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ARRAY_SIZE(pcm038_i2c_devices));
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mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
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#endif
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platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
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#ifdef CONFIG_MACH_PCM970_BASEBOARD
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pcm970_baseboard_init();
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#endif
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}
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static void __init pcm038_timer_init(void)
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{
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mx27_clocks_init(26000000);
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}
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static struct sys_timer pcm038_timer = {
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.init = pcm038_timer_init,
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};
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MACHINE_START(PCM038, "phyCORE-i.MX27")
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.phys_io = AIPI_BASE_ADDR,
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.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
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.boot_params = PHYS_OFFSET + 0x100,
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.map_io = mx27_map_io,
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.init_irq = mxc_init_irq,
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.init_machine = pcm038_init,
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.timer = &pcm038_timer,
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MACHINE_END
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