07500b0d85
A new born thread starts execution not in schedule but rather in ret_from_fork which results in it bypassing the part of the code to load a new context written in C which are the DSP context and the userlocal register which Linux uses for the TLS pointer. Frequently we were just getting away with this bug for a number of reasons: o Real world application scenarios are very unlikely to use clone or fork in blocks of DSP code. o Linux by default runs the child process right after the fork, so the child by luck will find all the right context in the DSP and userlocal registers. o So far the rdhwr instruction was emulated on all hardware so userlocal wasn't getting referenced at all and the emulation wasn't suffering from the issue since it gets it's value straight from the thread's thread_info. Fixed by moving the code to load the context from switch_to() to finish_arch_switch which will be called by newborn and old threads. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
222 lines
5.6 KiB
C
222 lines
5.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
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* Copyright (C) 1996 by Paul M. Antoine
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* Copyright (C) 1999 Silicon Graphics
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* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc.
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*/
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#ifndef _ASM_SYSTEM_H
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#define _ASM_SYSTEM_H
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#include <linux/types.h>
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#include <linux/irqflags.h>
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#include <asm/addrspace.h>
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#include <asm/barrier.h>
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#include <asm/cmpxchg.h>
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#include <asm/cpu-features.h>
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#include <asm/dsp.h>
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#include <asm/war.h>
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/*
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* switch_to(n) should switch tasks to task nr n, first
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* checking that n isn't the current task, in which case it does nothing.
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*/
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extern asmlinkage void *resume(void *last, void *next, void *next_ti);
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struct task_struct;
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#ifdef CONFIG_MIPS_MT_FPAFF
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/*
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* Handle the scheduler resume end of FPU affinity management. We do this
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* inline to try to keep the overhead down. If we have been forced to run on
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* a "CPU" with an FPU because of a previous high level of FP computation,
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* but did not actually use the FPU during the most recent time-slice (CU1
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* isn't set), we undo the restriction on cpus_allowed.
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*
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* We're not calling set_cpus_allowed() here, because we have no need to
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* force prompt migration - we're already switching the current CPU to a
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* different thread.
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*/
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#define __mips_mt_fpaff_switch_to(prev) \
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do { \
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struct thread_info *__prev_ti = task_thread_info(prev); \
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\
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if (cpu_has_fpu && \
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test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
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(!(KSTK_STATUS(prev) & ST0_CU1))) { \
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clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
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prev->cpus_allowed = prev->thread.user_cpus_allowed; \
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} \
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next->thread.emulated_fp = 0; \
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} while(0)
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#else
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#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
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#endif
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#define switch_to(prev, next, last) \
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do { \
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__mips_mt_fpaff_switch_to(prev); \
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if (cpu_has_dsp) \
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__save_dsp(prev); \
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(last) = resume(prev, next, task_thread_info(next)); \
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} while (0)
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#define finish_arch_switch(prev) \
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do { \
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if (cpu_has_dsp) \
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__restore_dsp(current); \
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if (cpu_has_userlocal) \
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write_c0_userlocal(current_thread_info()->tp_value); \
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} while (0)
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static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
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{
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__u32 retval;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long dummy;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %0, %3 # xchg_u32 \n"
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" .set mips0 \n"
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" move %2, %z4 \n"
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" .set mips3 \n"
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" sc %2, %1 \n"
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" beqzl %2, 1b \n"
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" .set mips0 \n"
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: "=&r" (retval), "=m" (*m), "=&r" (dummy)
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: "R" (*m), "Jr" (val)
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: "memory");
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} else if (cpu_has_llsc) {
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unsigned long dummy;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %0, %3 # xchg_u32 \n"
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" .set mips0 \n"
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" move %2, %z4 \n"
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" .set mips3 \n"
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" sc %2, %1 \n"
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" beqz %2, 2f \n"
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" .subsection 2 \n"
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"2: b 1b \n"
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" .previous \n"
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" .set mips0 \n"
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: "=&r" (retval), "=m" (*m), "=&r" (dummy)
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: "R" (*m), "Jr" (val)
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: "memory");
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} else {
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unsigned long flags;
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raw_local_irq_save(flags);
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retval = *m;
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*m = val;
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raw_local_irq_restore(flags); /* implies memory barrier */
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}
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smp_llsc_mb();
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return retval;
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}
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#ifdef CONFIG_64BIT
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static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
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{
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__u64 retval;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long dummy;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: lld %0, %3 # xchg_u64 \n"
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" move %2, %z4 \n"
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" scd %2, %1 \n"
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" beqzl %2, 1b \n"
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" .set mips0 \n"
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: "=&r" (retval), "=m" (*m), "=&r" (dummy)
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: "R" (*m), "Jr" (val)
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: "memory");
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} else if (cpu_has_llsc) {
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unsigned long dummy;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: lld %0, %3 # xchg_u64 \n"
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" move %2, %z4 \n"
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" scd %2, %1 \n"
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" beqz %2, 2f \n"
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" .subsection 2 \n"
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"2: b 1b \n"
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" .previous \n"
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" .set mips0 \n"
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: "=&r" (retval), "=m" (*m), "=&r" (dummy)
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: "R" (*m), "Jr" (val)
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: "memory");
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} else {
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unsigned long flags;
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raw_local_irq_save(flags);
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retval = *m;
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*m = val;
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raw_local_irq_restore(flags); /* implies memory barrier */
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}
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smp_llsc_mb();
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return retval;
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}
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#else
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extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
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#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
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#endif
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/* This function doesn't exist, so you'll get a linker error
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if something tries to do an invalid xchg(). */
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extern void __xchg_called_with_bad_pointer(void);
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 4:
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return __xchg_u32(ptr, x);
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case 8:
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return __xchg_u64(ptr, x);
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
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extern void set_handler(unsigned long offset, void *addr, unsigned long len);
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extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
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typedef void (*vi_handler_t)(void);
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extern void *set_vi_handler(int n, vi_handler_t addr);
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extern void *set_except_vector(int n, void *addr);
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extern unsigned long ebase;
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extern void per_cpu_trap_init(void);
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extern int stop_a_enabled;
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/*
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* See include/asm-ia64/system.h; prevents deadlock on SMP
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* systems.
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*/
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#define __ARCH_WANT_UNLOCKED_CTXSW
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extern unsigned long arch_align_stack(unsigned long sp);
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#endif /* _ASM_SYSTEM_H */
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