eb70e5ab8f
This adds EHCI host support to the chipidea driver. We want it to be part of the hdrc driver and not a standalone (sub-)driver module, as the structure of ehci-hcd.c suggests, so for chipidea controller we hack it to not provide platform-related code, but only the ehci hcd. The ehci-platform driver won't work for us here too, because the controller uses the same registers for both device and host mode and also otg-related bits, so it's not really possible to put ehci registers into a separate resource. This is not a pretty solution, but the alternative is exporting symbols from the chipidea driver to a ehci-chipidea driver and doing all the module refcounting. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
/*
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* bits.h - register bits of the ChipIdea USB IP core
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*
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* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
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*
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* Author: David Lopo
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DRIVERS_USB_CHIPIDEA_BITS_H
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#define __DRIVERS_USB_CHIPIDEA_BITS_H
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#include <linux/usb/ehci_def.h>
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/* HCCPARAMS */
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#define HCCPARAMS_LEN BIT(17)
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/* DCCPARAMS */
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#define DCCPARAMS_DEN (0x1F << 0)
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#define DCCPARAMS_DC BIT(7)
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#define DCCPARAMS_HC BIT(8)
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/* TESTMODE */
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#define TESTMODE_FORCE BIT(0)
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/* USBCMD */
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#define USBCMD_RS BIT(0)
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#define USBCMD_RST BIT(1)
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#define USBCMD_SUTW BIT(13)
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#define USBCMD_ATDTW BIT(14)
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/* USBSTS & USBINTR */
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#define USBi_UI BIT(0)
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#define USBi_UEI BIT(1)
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#define USBi_PCI BIT(2)
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#define USBi_URI BIT(6)
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#define USBi_SLI BIT(8)
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/* DEVICEADDR */
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#define DEVICEADDR_USBADRA BIT(24)
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#define DEVICEADDR_USBADR (0x7FUL << 25)
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/* PORTSC */
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#define PORTSC_FPR BIT(6)
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#define PORTSC_SUSP BIT(7)
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#define PORTSC_HSP BIT(9)
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#define PORTSC_PTC (0x0FUL << 16)
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/* DEVLC */
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#define DEVLC_PSPD (0x03UL << 25)
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#define DEVLC_PSPD_HS (0x02UL << 25)
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/* OTGSC */
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#define OTGSC_IDPU BIT(5)
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#define OTGSC_ID BIT(8)
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#define OTGSC_AVV BIT(9)
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#define OTGSC_ASV BIT(10)
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#define OTGSC_BSV BIT(11)
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#define OTGSC_BSE BIT(12)
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#define OTGSC_IDIS BIT(16)
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#define OTGSC_AVVIS BIT(17)
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#define OTGSC_ASVIS BIT(18)
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#define OTGSC_BSVIS BIT(19)
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#define OTGSC_BSEIS BIT(20)
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#define OTGSC_IDIE BIT(24)
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#define OTGSC_AVVIE BIT(25)
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#define OTGSC_ASVIE BIT(26)
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#define OTGSC_BSVIE BIT(27)
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#define OTGSC_BSEIE BIT(28)
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/* USBMODE */
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#define USBMODE_CM (0x03UL << 0)
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#define USBMODE_CM_DC (0x02UL << 0)
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#define USBMODE_SLOM BIT(3)
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#define USBMODE_CI_SDIS BIT(4)
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/* ENDPTCTRL */
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#define ENDPTCTRL_RXS BIT(0)
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#define ENDPTCTRL_RXT (0x03UL << 2)
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#define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */
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#define ENDPTCTRL_RXE BIT(7)
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#define ENDPTCTRL_TXS BIT(16)
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#define ENDPTCTRL_TXT (0x03UL << 18)
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#define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */
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#define ENDPTCTRL_TXE BIT(23)
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#endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */
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