effbc4fd8e
Daniel Vetter wrote First pull request for 3.5-next, slightly large than usual because new things kept coming in since the last pull for 3.4. Highlights: - first batch of hw enablement for vlv (Jesse et al) and hsw (Eugeni). pci ids are not yet added, and there's still quite a few patches to merge (mostly modesetting). To make QA easier I've decided to merge this stuff in pieces. - loads of cleanups and prep patches spurred by the above. Especially vlv is a real frankenstein chip, but also hsw is stretching our driver's code design. Expect more to come in this area for 3.5. - more gmbus fixes, cleanups and improvements by Daniel Kurtz. Again, there are more patches needed (and some already queued up), but I wanted to split this a bit for better testing. - pwrite/pread rework and retuning. This series has been in the works for a few months already and a lot of i-g-t tests have been created for it. Now it's finally ready to be merged. Note that one patch in this series touches include/pagemap.h, that patch is acked-by akpm. - reduce mappable pressure and relocation throughput improvements from Chris. - mmap offset exhaustion mitigation by Chris Wilson. - a start at figuring out which codepaths in our messy dri1/ums+gem/kms driver we actually need to support by bailing out of unsupported case. The driver now refuses to load without kms on gen6+ and disallows a few ioctls that userspace never used in certain cases. More of this will definitely come. - More decoupling of global gtt and ppgtt. - Improved dual-link lvds detection by Takashi Iwai. - Shut up the compiler + plus fix the fallout (Ben) - Inverted panel brightness handling (mostly Acer manages to break things in this way). - Small fixlets and adjustements and some minor things to help debugging. Regression-wise QA reported quite a few issues on ivb, but all of them turned out to be hw stability issues which are already fixed in drm-intel-fixes (QA runs the nightly regression tests on -next alone, without -fixes automatically merged in). There's still one issue open on snb, it looks like occlusion query writes are not quite as cache coherent as we've expected. With some of the pwrite adjustements we can now reliably hit this. Kernel workaround for it is in the works." * 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-intel: (101 commits) drm/i915: VCS is not the last ring drm/i915: Add a dual link lvds quirk for MacBook Pro 8,2 drm/i915: make quirks more verbose drm/i915: dump the DMA fetch addr register on pre-gen6 drm/i915/sdvo: Include YRPB as an additional TV output type drm/i915: disallow gem init ioctl on ilk drm/i915: refuse to load on gen6+ without kms drm/i915: extract gt interrupt handler drm/i915: use render gen to switch ring irq functions drm/i915: rip out old HWSTAM missed irq WA for vlv drm/i915: open code gen6+ ring irqs drm/i915: ring irq cleanups drm/i915: add SFUSE_STRAP registers for digital port detection drm/i915: add WM_LINETIME registers drm/i915: add WRPLL clocks drm/i915: add LCPLL control registers drm/i915: add SSC offsets for SBI access drm/i915: add port clock selection support for HSW drm/i915: add S PLL control drm/i915: add PIXCLK_GATE register ... Conflicts: drivers/char/agp/intel-agp.h drivers/char/agp/intel-gtt.c drivers/gpu/drm/i915/i915_debugfs.c
256 lines
9.5 KiB
C
256 lines
9.5 KiB
C
/*
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* Common Intel AGPGART and GTT definitions.
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*/
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#ifndef _INTEL_AGP_H
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#define _INTEL_AGP_H
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/* Intel registers */
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#define INTEL_APSIZE 0xb4
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#define INTEL_ATTBASE 0xb8
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#define INTEL_AGPCTRL 0xb0
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#define INTEL_NBXCFG 0x50
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#define INTEL_ERRSTS 0x91
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/* Intel i830 registers */
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#define I830_GMCH_CTRL 0x52
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#define I830_GMCH_ENABLED 0x4
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#define I830_GMCH_MEM_MASK 0x1
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#define I830_GMCH_MEM_64M 0x1
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#define I830_GMCH_MEM_128M 0
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#define I830_GMCH_GMS_MASK 0x70
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#define I830_GMCH_GMS_DISABLED 0x00
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#define I830_GMCH_GMS_LOCAL 0x10
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#define I830_GMCH_GMS_STOLEN_512 0x20
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#define I830_GMCH_GMS_STOLEN_1024 0x30
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#define I830_GMCH_GMS_STOLEN_8192 0x40
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#define I830_RDRAM_CHANNEL_TYPE 0x03010
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#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
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#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
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/* This one is for I830MP w. an external graphic card */
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#define INTEL_I830_ERRSTS 0x92
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/* Intel 855GM/852GM registers */
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#define I855_GMCH_GMS_MASK 0xF0
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#define I855_GMCH_GMS_STOLEN_0M 0x0
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#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
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#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
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#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
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#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
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#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
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#define I85X_CAPID 0x44
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#define I85X_VARIANT_MASK 0x7
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#define I85X_VARIANT_SHIFT 5
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#define I855_GME 0x0
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#define I855_GM 0x4
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#define I852_GME 0x2
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#define I852_GM 0x5
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/* Intel i845 registers */
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#define INTEL_I845_AGPM 0x51
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#define INTEL_I845_ERRSTS 0xc8
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/* Intel i860 registers */
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#define INTEL_I860_MCHCFG 0x50
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#define INTEL_I860_ERRSTS 0xc8
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/* Intel i810 registers */
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#define I810_GMADDR 0x10
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#define I810_MMADDR 0x14
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#define I810_PTE_BASE 0x10000
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#define I810_PTE_MAIN_UNCACHED 0x00000000
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#define I810_PTE_LOCAL 0x00000002
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#define I810_PTE_VALID 0x00000001
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#define I830_PTE_SYSTEM_CACHED 0x00000006
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/* GT PTE cache control fields */
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#define GEN6_PTE_UNCACHED 0x00000002
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#define GEN6_PTE_LLC 0x00000004
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#define GEN6_PTE_LLC_MLC 0x00000006
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#define GEN6_PTE_GFDT 0x00000008
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#define I810_SMRAM_MISCC 0x70
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#define I810_GFX_MEM_WIN_SIZE 0x00010000
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#define I810_GFX_MEM_WIN_32M 0x00010000
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#define I810_GMS 0x000000c0
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#define I810_GMS_DISABLE 0x00000000
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#define I810_PGETBL_CTL 0x2020
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#define I810_PGETBL_ENABLED 0x00000001
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/* Note: PGETBL_CTL2 has a different offset on G33. */
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#define I965_PGETBL_CTL2 0x20c4
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#define I965_PGETBL_SIZE_MASK 0x0000000e
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#define I965_PGETBL_SIZE_512KB (0 << 1)
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#define I965_PGETBL_SIZE_256KB (1 << 1)
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#define I965_PGETBL_SIZE_128KB (2 << 1)
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#define I965_PGETBL_SIZE_1MB (3 << 1)
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#define I965_PGETBL_SIZE_2MB (4 << 1)
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#define I965_PGETBL_SIZE_1_5MB (5 << 1)
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#define G33_GMCH_SIZE_MASK (3 << 8)
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#define G33_GMCH_SIZE_1M (1 << 8)
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#define G33_GMCH_SIZE_2M (2 << 8)
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#define G4x_GMCH_SIZE_MASK (0xf << 8)
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#define G4x_GMCH_SIZE_1M (0x1 << 8)
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#define G4x_GMCH_SIZE_2M (0x3 << 8)
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#define G4x_GMCH_SIZE_VT_EN (0x8 << 8)
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#define G4x_GMCH_SIZE_VT_1M (G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN)
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#define G4x_GMCH_SIZE_VT_1_5M ((0x2 << 8) | G4x_GMCH_SIZE_VT_EN)
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#define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
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#define GFX_FLSH_CNTL 0x2170 /* 915+ */
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#define GFX_FLSH_CNTL_VLV 0x101008
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#define I810_DRAM_CTL 0x3000
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#define I810_DRAM_ROW_0 0x00000001
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#define I810_DRAM_ROW_0_SDRAM 0x00000001
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/* Intel 815 register */
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#define INTEL_815_APCONT 0x51
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#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
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/* Intel i820 registers */
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#define INTEL_I820_RDCR 0x51
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#define INTEL_I820_ERRSTS 0xc8
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/* Intel i840 registers */
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#define INTEL_I840_MCHCFG 0x50
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#define INTEL_I840_ERRSTS 0xc8
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/* Intel i850 registers */
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#define INTEL_I850_MCHCFG 0x50
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#define INTEL_I850_ERRSTS 0xc8
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/* intel 915G registers */
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#define I915_GMADDR 0x18
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#define I915_MMADDR 0x10
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#define I915_PTEADDR 0x1C
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#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
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#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
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#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
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#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
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#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
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#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
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#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
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#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
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#define I915_IFPADDR 0x60
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#define I830_HIC 0x70
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/* Intel 965G registers */
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#define I965_MSAC 0x62
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#define I965_IFPADDR 0x70
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/* Intel 7505 registers */
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#define INTEL_I7505_APSIZE 0x74
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#define INTEL_I7505_NCAPID 0x60
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#define INTEL_I7505_NISTAT 0x6c
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#define INTEL_I7505_ATTBASE 0x78
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#define INTEL_I7505_ERRSTS 0x42
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#define INTEL_I7505_AGPCTRL 0x70
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#define INTEL_I7505_MCHCFG 0x50
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#define SNB_GMCH_CTRL 0x50
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#define SNB_GMCH_GMS_STOLEN_MASK 0xF8
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#define SNB_GMCH_GMS_STOLEN_32M (1 << 3)
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#define SNB_GMCH_GMS_STOLEN_64M (2 << 3)
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#define SNB_GMCH_GMS_STOLEN_96M (3 << 3)
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#define SNB_GMCH_GMS_STOLEN_128M (4 << 3)
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#define SNB_GMCH_GMS_STOLEN_160M (5 << 3)
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#define SNB_GMCH_GMS_STOLEN_192M (6 << 3)
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#define SNB_GMCH_GMS_STOLEN_224M (7 << 3)
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#define SNB_GMCH_GMS_STOLEN_256M (8 << 3)
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#define SNB_GMCH_GMS_STOLEN_288M (9 << 3)
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#define SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
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#define SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
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#define SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
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#define SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
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#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
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#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
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#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
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#define SNB_GTT_SIZE_0M (0 << 8)
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#define SNB_GTT_SIZE_1M (1 << 8)
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#define SNB_GTT_SIZE_2M (2 << 8)
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#define SNB_GTT_SIZE_MASK (3 << 8)
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/* pci devices ids */
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#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
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#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
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#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
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#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
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#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
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#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
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#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
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#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
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#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
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#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
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#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
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#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
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#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
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#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
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#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
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#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
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#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010
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#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011
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#define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000
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#define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001
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#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
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#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
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#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
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#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
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#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
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#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
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#define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40
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#define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
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#define PCI_DEVICE_ID_INTEL_B43_1_HB 0x2E90
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#define PCI_DEVICE_ID_INTEL_B43_1_IG 0x2E92
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#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
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#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
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#define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00
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#define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02
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#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
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#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
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#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
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#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
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#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
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#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 /* Desktop */
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG 0x0102
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG 0x0112
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG 0x0122
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 /* Mobile */
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG 0x0106
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG 0x0116
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB 0x0150 /* Desktop */
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG 0x0152
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG 0x0162
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB 0x0154 /* Mobile */
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG 0x0156
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A
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#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB 0x0F00 /* VLV1 */
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#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG 0x0F30
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#define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */
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#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG 0x0402
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#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG 0x0412
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#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */
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#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG 0x0406
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#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG 0x0416
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#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */
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#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG 0x040a
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#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG 0x041a
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#define PCI_DEVICE_ID_INTEL_HASWELL_SDV 0x0c16 /* SDV */
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#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04
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int intel_gmch_probe(struct pci_dev *pdev,
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struct agp_bridge_data *bridge);
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void intel_gmch_remove(struct pci_dev *pdev);
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#endif
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