a227fd7db7
Partial support for DaVinci DM355, on the EVM board; peripheral
mode should work, once mainline merges DM355 support. Missing:
(a) renumbering the GPIO for DRVVBUS on the DM6446 EVM,
when DAVINCI_N_GPIO increases;
(b) disabling DM355_DEEPSLEEP.DRVVBUS_OVERRIDE so VBUS is
driven according to the ID signal, if cpu_is_..._dm355()
The new PHY control bits are ignored on DM6446.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
107 lines
3.3 KiB
C
107 lines
3.3 KiB
C
/*
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* Copyright (C) 2005-2006 by Texas Instruments
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*
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* The Inventra Controller Driver for Linux is free software; you
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* can redistribute it and/or modify it under the terms of the GNU
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* General Public License version 2 as published by the Free Software
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* Foundation.
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*/
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#ifndef __MUSB_HDRDF_H__
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#define __MUSB_HDRDF_H__
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/*
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* DaVinci-specific definitions
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*/
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/* Integrated highspeed/otg PHY */
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#define USBPHY_CTL_PADDR (DAVINCI_SYSTEM_MODULE_BASE + 0x34)
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#define USBPHY_DATAPOL BIT(11) /* (dm355) switch D+/D- */
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#define USBPHY_PHYCLKGD BIT(8)
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#define USBPHY_SESNDEN BIT(7) /* v(sess_end) comparator */
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#define USBPHY_VBDTCTEN BIT(6) /* v(bus) comparator */
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#define USBPHY_VBUSSENS BIT(5) /* (dm355,ro) is vbus > 0.5V */
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#define USBPHY_PHYPLLON BIT(4) /* override pll suspend */
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#define USBPHY_CLKO1SEL BIT(3)
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#define USBPHY_OSCPDWN BIT(2)
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#define USBPHY_OTGPDWN BIT(1)
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#define USBPHY_PHYPDWN BIT(0)
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#define DM355_DEEPSLEEP_PADDR (DAVINCI_SYSTEM_MODULE_BASE + 0x48)
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#define DRVVBUS_FORCE BIT(2)
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#define DRVVBUS_OVERRIDE BIT(1)
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/* For now include usb OTG module registers here */
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#define DAVINCI_USB_VERSION_REG 0x00
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#define DAVINCI_USB_CTRL_REG 0x04
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#define DAVINCI_USB_STAT_REG 0x08
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#define DAVINCI_RNDIS_REG 0x10
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#define DAVINCI_AUTOREQ_REG 0x14
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#define DAVINCI_USB_INT_SOURCE_REG 0x20
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#define DAVINCI_USB_INT_SET_REG 0x24
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#define DAVINCI_USB_INT_SRC_CLR_REG 0x28
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#define DAVINCI_USB_INT_MASK_REG 0x2c
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#define DAVINCI_USB_INT_MASK_SET_REG 0x30
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#define DAVINCI_USB_INT_MASK_CLR_REG 0x34
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#define DAVINCI_USB_INT_SRC_MASKED_REG 0x38
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#define DAVINCI_USB_EOI_REG 0x3c
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#define DAVINCI_USB_EOI_INTVEC 0x40
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/* BEGIN CPPI-generic (?) */
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/* CPPI related registers */
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#define DAVINCI_TXCPPI_CTRL_REG 0x80
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#define DAVINCI_TXCPPI_TEAR_REG 0x84
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#define DAVINCI_CPPI_EOI_REG 0x88
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#define DAVINCI_CPPI_INTVEC_REG 0x8c
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#define DAVINCI_TXCPPI_MASKED_REG 0x90
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#define DAVINCI_TXCPPI_RAW_REG 0x94
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#define DAVINCI_TXCPPI_INTENAB_REG 0x98
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#define DAVINCI_TXCPPI_INTCLR_REG 0x9c
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#define DAVINCI_RXCPPI_CTRL_REG 0xC0
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#define DAVINCI_RXCPPI_MASKED_REG 0xD0
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#define DAVINCI_RXCPPI_RAW_REG 0xD4
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#define DAVINCI_RXCPPI_INTENAB_REG 0xD8
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#define DAVINCI_RXCPPI_INTCLR_REG 0xDC
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#define DAVINCI_RXCPPI_BUFCNT0_REG 0xE0
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#define DAVINCI_RXCPPI_BUFCNT1_REG 0xE4
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#define DAVINCI_RXCPPI_BUFCNT2_REG 0xE8
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#define DAVINCI_RXCPPI_BUFCNT3_REG 0xEC
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/* CPPI state RAM entries */
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#define DAVINCI_CPPI_STATERAM_BASE_OFFSET 0x100
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#define DAVINCI_TXCPPI_STATERAM_OFFSET(chnum) \
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(DAVINCI_CPPI_STATERAM_BASE_OFFSET + ((chnum) * 0x40))
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#define DAVINCI_RXCPPI_STATERAM_OFFSET(chnum) \
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(DAVINCI_CPPI_STATERAM_BASE_OFFSET + 0x20 + ((chnum) * 0x40))
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/* CPPI masks */
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#define DAVINCI_DMA_CTRL_ENABLE 1
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#define DAVINCI_DMA_CTRL_DISABLE 0
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#define DAVINCI_DMA_ALL_CHANNELS_ENABLE 0xF
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#define DAVINCI_DMA_ALL_CHANNELS_DISABLE 0xF
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/* END CPPI-generic (?) */
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#define DAVINCI_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
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#define DAVINCI_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
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#define DAVINCI_USB_USBINT_SHIFT 16
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#define DAVINCI_USB_TXINT_SHIFT 0
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#define DAVINCI_USB_RXINT_SHIFT 8
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#define DAVINCI_INTR_DRVVBUS 0x0100
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#define DAVINCI_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
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#define DAVINCI_USB_TXINT_MASK \
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(DAVINCI_USB_TX_ENDPTS_MASK << DAVINCI_USB_TXINT_SHIFT)
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#define DAVINCI_USB_RXINT_MASK \
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(DAVINCI_USB_RX_ENDPTS_MASK << DAVINCI_USB_RXINT_SHIFT)
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#define DAVINCI_BASE_OFFSET 0x400
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#endif /* __MUSB_HDRDF_H__ */
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