456 lines
12 KiB
C
456 lines
12 KiB
C
/*
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* Copyright (C) 2007 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_ramht.h"
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#include "nouveau_grctx.h"
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static void
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nv50_graph_init_reset(struct drm_device *dev)
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{
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uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
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NV_DEBUG(dev, "\n");
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | pmc_e);
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}
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static void
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nv50_graph_init_intr(struct drm_device *dev)
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{
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NV_DEBUG(dev, "\n");
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nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
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nv_wr32(dev, 0x400138, 0xffffffff);
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nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
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}
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static void
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nv50_graph_init_regs__nv(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t units = nv_rd32(dev, 0x1540);
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int i;
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NV_DEBUG(dev, "\n");
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nv_wr32(dev, 0x400804, 0xc0000000);
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nv_wr32(dev, 0x406800, 0xc0000000);
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nv_wr32(dev, 0x400c04, 0xc0000000);
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nv_wr32(dev, 0x401800, 0xc0000000);
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nv_wr32(dev, 0x405018, 0xc0000000);
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nv_wr32(dev, 0x402000, 0xc0000000);
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for (i = 0; i < 16; i++) {
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if (units & 1 << i) {
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if (dev_priv->chipset < 0xa0) {
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nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
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nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
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nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
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} else {
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nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
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nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
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nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
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}
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}
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}
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nv_wr32(dev, 0x400108, 0xffffffff);
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nv_wr32(dev, 0x400824, 0x00004000);
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nv_wr32(dev, 0x400500, 0x00010001);
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}
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static void
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nv50_graph_init_regs(struct drm_device *dev)
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{
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NV_DEBUG(dev, "\n");
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nv_wr32(dev, NV04_PGRAPH_DEBUG_3,
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(1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */);
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nv_wr32(dev, 0x402ca8, 0x800);
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}
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static int
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nv50_graph_init_ctxctl(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_grctx ctx = {};
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uint32_t *cp;
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int i;
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NV_DEBUG(dev, "\n");
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cp = kmalloc(512 * 4, GFP_KERNEL);
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if (!cp) {
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NV_ERROR(dev, "failed to allocate ctxprog\n");
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dev_priv->engine.graph.accel_blocked = true;
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return 0;
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}
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ctx.dev = dev;
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ctx.mode = NOUVEAU_GRCTX_PROG;
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ctx.data = cp;
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ctx.ctxprog_max = 512;
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if (!nv50_grctx_init(&ctx)) {
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dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
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for (i = 0; i < ctx.ctxprog_len; i++)
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
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} else {
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dev_priv->engine.graph.accel_blocked = true;
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}
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kfree(cp);
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nv_wr32(dev, 0x400320, 4);
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
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return 0;
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}
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int
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nv50_graph_init(struct drm_device *dev)
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{
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int ret;
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NV_DEBUG(dev, "\n");
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nv50_graph_init_reset(dev);
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nv50_graph_init_regs__nv(dev);
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nv50_graph_init_regs(dev);
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nv50_graph_init_intr(dev);
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ret = nv50_graph_init_ctxctl(dev);
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if (ret)
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return ret;
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return 0;
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}
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void
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nv50_graph_takedown(struct drm_device *dev)
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{
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NV_DEBUG(dev, "\n");
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}
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void
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nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
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{
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const uint32_t mask = 0x00010001;
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if (enabled)
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nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
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else
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nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
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}
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struct nouveau_channel *
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nv50_graph_channel(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t inst;
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int i;
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/* Be sure we're not in the middle of a context switch or bad things
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* will happen, such as unloading the wrong pgraph context.
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*/
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if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
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NV_ERROR(dev, "Ctxprog is still running\n");
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inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
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if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
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return NULL;
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inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
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for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
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struct nouveau_channel *chan = dev_priv->fifos[i];
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if (chan && chan->ramin && chan->ramin->vinst == inst)
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return chan;
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}
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return NULL;
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}
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int
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nv50_graph_create_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramin = chan->ramin;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_grctx ctx = {};
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int hdr, ret;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
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if (ret)
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return ret;
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hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
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nv_wo32(ramin, hdr + 0x00, 0x00190002);
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nv_wo32(ramin, hdr + 0x04, chan->ramin_grctx->vinst +
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pgraph->grctx_size - 1);
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nv_wo32(ramin, hdr + 0x08, chan->ramin_grctx->vinst);
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nv_wo32(ramin, hdr + 0x0c, 0);
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nv_wo32(ramin, hdr + 0x10, 0);
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nv_wo32(ramin, hdr + 0x14, 0x00010000);
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ctx.dev = chan->dev;
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ctx.mode = NOUVEAU_GRCTX_VALS;
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ctx.data = chan->ramin_grctx;
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nv50_grctx_init(&ctx);
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nv_wo32(chan->ramin_grctx, 0x00000, chan->ramin->vinst >> 12);
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dev_priv->engine.instmem.flush(dev);
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return 0;
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}
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void
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nv50_graph_destroy_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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if (!chan->ramin)
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return;
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for (i = hdr; i < hdr + 24; i += 4)
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nv_wo32(chan->ramin, i, 0);
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dev_priv->engine.instmem.flush(dev);
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nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
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}
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static int
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nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
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{
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uint32_t fifo = nv_rd32(dev, 0x400500);
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nv_wr32(dev, 0x400500, fifo & ~1);
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nv_wr32(dev, 0x400784, inst);
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nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
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nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
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nv_wr32(dev, 0x400040, 0xffffffff);
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(void)nv_rd32(dev, 0x400040);
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nv_wr32(dev, 0x400040, 0x00000000);
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nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
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if (nouveau_wait_for_idle(dev))
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nv_wr32(dev, 0x40032c, inst | (1<<31));
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nv_wr32(dev, 0x400500, fifo);
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return 0;
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}
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int
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nv50_graph_load_context(struct nouveau_channel *chan)
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{
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uint32_t inst = chan->ramin->vinst >> 12;
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NV_DEBUG(chan->dev, "ch%d\n", chan->id);
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return nv50_graph_do_load_context(chan->dev, inst);
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}
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int
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nv50_graph_unload_context(struct drm_device *dev)
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{
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uint32_t inst;
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inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
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if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
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return 0;
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inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
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nouveau_wait_for_idle(dev);
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nv_wr32(dev, 0x400784, inst);
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nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
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nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
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nouveau_wait_for_idle(dev);
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nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
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return 0;
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}
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void
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nv50_graph_context_switch(struct drm_device *dev)
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{
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uint32_t inst;
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nv50_graph_unload_context(dev);
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inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
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inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
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nv50_graph_do_load_context(dev, inst);
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nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
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NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
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}
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static int
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nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan, int grclass,
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int mthd, uint32_t data)
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{
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struct nouveau_gpuobj *gpuobj;
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gpuobj = nouveau_ramht_find(chan, data);
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if (!gpuobj)
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return -ENOENT;
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if (nouveau_notifier_offset(gpuobj, NULL))
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return -EINVAL;
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chan->nvsw.vblsem = gpuobj;
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chan->nvsw.vblsem_offset = ~0;
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return 0;
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}
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static int
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nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan, int grclass,
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int mthd, uint32_t data)
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{
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if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
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return -ERANGE;
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chan->nvsw.vblsem_offset = data >> 2;
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return 0;
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}
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static int
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nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan, int grclass,
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int mthd, uint32_t data)
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{
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chan->nvsw.vblsem_rval = data;
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return 0;
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}
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static int
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nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan, int grclass,
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int mthd, uint32_t data)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
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return -EINVAL;
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if (!(nv_rd32(dev, NV50_PDISPLAY_INTR_EN) &
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NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data))) {
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nv_wr32(dev, NV50_PDISPLAY_INTR_1,
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NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(data));
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nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
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NV50_PDISPLAY_INTR_EN) |
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NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data));
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}
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list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
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return 0;
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}
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static struct nouveau_pgraph_object_method nv50_graph_nvsw_methods[] = {
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{ 0x018c, nv50_graph_nvsw_dma_vblsem },
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{ 0x0400, nv50_graph_nvsw_vblsem_offset },
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{ 0x0404, nv50_graph_nvsw_vblsem_release_val },
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{ 0x0408, nv50_graph_nvsw_vblsem_release },
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{}
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};
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struct nouveau_pgraph_object_class nv50_graph_grclass[] = {
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{ 0x506e, true, nv50_graph_nvsw_methods }, /* nvsw */
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{ 0x0030, false, NULL }, /* null */
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{ 0x5039, false, NULL }, /* m2mf */
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{ 0x502d, false, NULL }, /* 2d */
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{ 0x50c0, false, NULL }, /* compute */
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{ 0x85c0, false, NULL }, /* compute (nva3, nva5, nva8) */
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{ 0x5097, false, NULL }, /* tesla (nv50) */
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{ 0x8297, false, NULL }, /* tesla (nv8x/nv9x) */
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{ 0x8397, false, NULL }, /* tesla (nva0, nvaa, nvac) */
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{ 0x8597, false, NULL }, /* tesla (nva3, nva5, nva8) */
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{}
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};
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void
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nv50_graph_tlb_flush(struct drm_device *dev)
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{
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nv50_vm_flush(dev, 0);
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}
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void
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nv86_graph_tlb_flush(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
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bool idle, timeout = false;
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unsigned long flags;
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u64 start;
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u32 tmp;
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
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start = ptimer->read(dev);
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do {
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idle = true;
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for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
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if ((tmp & 7) == 1)
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idle = false;
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}
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for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
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if ((tmp & 7) == 1)
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idle = false;
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}
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for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
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if ((tmp & 7) == 1)
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idle = false;
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}
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} while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
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if (timeout) {
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NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
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"0x%08x 0x%08x 0x%08x 0x%08x\n",
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nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
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nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
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}
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nv50_vm_flush(dev, 0);
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nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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}
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