78 lines
1.7 KiB
C
78 lines
1.7 KiB
C
#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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int
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nv50_fb_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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/* Not a clue what this is exactly. Without pointing it at a
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* scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
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* cause IOMMU "read from address 0" errors (rh#561267)
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*/
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nv_wr32(dev, 0x100c08, dev_priv->gart_info.sg_dummy_bus >> 8);
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/* This is needed to get meaningful information from 100c90
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* on traps. No idea what these values mean exactly. */
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switch (dev_priv->chipset) {
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case 0x50:
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nv_wr32(dev, 0x100c90, 0x0707ff);
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break;
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case 0xa3:
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case 0xa5:
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case 0xa8:
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nv_wr32(dev, 0x100c90, 0x0d0fff);
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break;
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default:
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nv_wr32(dev, 0x100c90, 0x1d07ff);
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break;
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}
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return 0;
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}
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void
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nv50_fb_takedown(struct drm_device *dev)
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{
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}
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void
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nv50_fb_vm_trap(struct drm_device *dev, int display, const char *name)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 trap[6], idx, chinst;
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int i, ch;
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idx = nv_rd32(dev, 0x100c90);
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if (!(idx & 0x80000000))
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return;
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idx &= 0x00ffffff;
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for (i = 0; i < 6; i++) {
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nv_wr32(dev, 0x100c90, idx | i << 24);
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trap[i] = nv_rd32(dev, 0x100c94);
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}
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nv_wr32(dev, 0x100c90, idx | 0x80000000);
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if (!display)
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return;
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chinst = (trap[2] << 16) | trap[1];
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for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) {
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struct nouveau_channel *chan = dev_priv->fifos[ch];
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if (!chan || !chan->ramin)
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continue;
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if (chinst == chan->ramin->vinst >> 12)
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break;
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}
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NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x "
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"channel %d (0x%08x)\n",
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name, (trap[5] & 0x100 ? "read" : "write"),
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trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff,
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trap[0], ch, chinst);
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}
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