1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
100 lines
2.8 KiB
ArmAsm
100 lines
2.8 KiB
ArmAsm
#include <asm/hardware.h>
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@ Code for DMA with the 1772 fdc
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.text
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.global fdc1772_dataaddr
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fdc1772_fiqdata:
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@ Number of bytes left to DMA
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.global fdc1772_bytestogo
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fdc1772_bytestogo:
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.word 0
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@ Place to put/get data from in DMA
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.global fdc1772_dataaddr
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fdc1772_dataaddr:
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.word 0
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.global fdc1772_fdc_int_done
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fdc1772_fdc_int_done:
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.word 0
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.global fdc1772_comendstatus
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fdc1772_comendstatus:
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.word 0
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@ We hang this off DMA channel 1
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.global fdc1772_comendhandler
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fdc1772_comendhandler:
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mov r8,#IOC_BASE
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ldrb r9,[r8,#0x34] @ IOC FIQ status
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tst r9,#2
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subeqs pc,r14,#4 @ should I leave a space here
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orr r9,r8,#0x10000 @ FDC base
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adr r8,fdc1772_fdc_int_done
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ldrb r10,[r9,#0] @ FDC status
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mov r9,#1 @ Got a FIQ flag
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stmia r8,{r9,r10}
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subs pc,r14,#4
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.global fdc1772_dma_read
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fdc1772_dma_read:
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mov r8,#IOC_BASE
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ldrb r9,[r8,#0x34] @ IOC FIQ status
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tst r9,#1
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beq fdc1772_dma_read_notours
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orr r8,r8,#0x10000 @ FDC base
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ldrb r10,[r8,#0xc] @ Read from FDC data reg (also clears interrupt)
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ldmia r11,{r8,r9}
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subs r8,r8,#1 @ One less byte to go
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@ If there was somewhere for this data to go then store it and update pointers
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strplb r10,[r9],#1 @ Store the data and increment the pointer
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stmplia r11,{r8,r9} @ Update count/pointers
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@ Handle any other interrupts if there are any
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fdc1772_dma_read_notours:
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@ Cant branch because this code has been copied down to the FIQ vector
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ldr pc,[pc,#-4]
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.word fdc1772_comendhandler
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.global fdc1772_dma_read_end
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fdc1772_dma_read_end:
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.global fdc1772_dma_write
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fdc1772_dma_write:
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mov r8,#IOC_BASE
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ldrb r9,[r8,#0x34] @ IOC FIQ status
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tst r9,#1
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beq fdc1772_dma_write_notours
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orr r8,r8,#0x10000 @ FDC base
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ldmia r11,{r9,r10}
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subs r9,r9,#1 @ One less byte to go
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@ If there really is some data then get it, store it and update count
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ldrplb r12,[r10],#1
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strplb r12,[r8,#0xc] @ write it to FDC data reg
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stmplia r11,{r9,r10} @ Update count and pointer - should clear interrupt
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@ Handle any other interrupts
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fdc1772_dma_write_notours:
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@ Cant branch because this code has been copied down to the FIQ vector
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ldr pc,[pc,#-4]
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.word fdc1772_comendhandler
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.global fdc1772_dma_write_end
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fdc1772_dma_write_end:
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@ Setup the FIQ R11 to point to the data and store the count, address
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@ for this dma
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@ R0=count
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@ R1=address
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.global fdc1772_setupdma
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fdc1772_setupdma:
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@ The big job is flipping in and out of FIQ mode
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adr r2,fdc1772_fiqdata @ This is what we really came here for
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stmia r2,{r0,r1}
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mov r3, pc
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teqp pc,#0x0c000001 @ Disable FIQs, IRQs and switch to FIQ mode
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mov r0,r0 @ NOP
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mov r11,r2
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teqp r3,#0 @ Normal mode
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mov r0,r0 @ NOP
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mov pc,r14
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