8263a67e16
This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
59 lines
1.2 KiB
C
59 lines
1.2 KiB
C
#ifndef __ASM_SH_MMU_CONTEXT_32_H
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#define __ASM_SH_MMU_CONTEXT_32_H
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/*
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* Destroy context related info for an mm_struct that is about
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* to be put to rest.
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*/
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static inline void destroy_context(struct mm_struct *mm)
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{
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/* Do nothing */
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}
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#ifdef CONFIG_CPU_HAS_PTEAEX
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static inline void set_asid(unsigned long asid)
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{
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__raw_writel(asid, MMU_PTEAEX);
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}
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static inline unsigned long get_asid(void)
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{
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return __raw_readl(MMU_PTEAEX) & MMU_CONTEXT_ASID_MASK;
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}
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#else
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static inline void set_asid(unsigned long asid)
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{
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unsigned long __dummy;
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__asm__ __volatile__ ("mov.l %2, %0\n\t"
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"and %3, %0\n\t"
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"or %1, %0\n\t"
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"mov.l %0, %2"
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: "=&r" (__dummy)
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: "r" (asid), "m" (__m(MMU_PTEH)),
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"r" (0xffffff00));
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}
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static inline unsigned long get_asid(void)
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{
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unsigned long asid;
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__asm__ __volatile__ ("mov.l %1, %0"
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: "=r" (asid)
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: "m" (__m(MMU_PTEH)));
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asid &= MMU_CONTEXT_ASID_MASK;
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return asid;
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}
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#endif /* CONFIG_CPU_HAS_PTEAEX */
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/* MMU_TTB is used for optimizing the fault handling. */
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static inline void set_TTB(pgd_t *pgd)
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{
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ctrl_outl((unsigned long)pgd, MMU_TTB);
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}
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static inline pgd_t *get_TTB(void)
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{
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return (pgd_t *)ctrl_inl(MMU_TTB);
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}
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#endif /* __ASM_SH_MMU_CONTEXT_32_H */
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