be020f8618
Require all callers of abort macros to specify the registers to be used. This improves the documentation at the callsites as to which registers are being used by this assembly code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
48 lines
1.4 KiB
ArmAsm
48 lines
1.4 KiB
ArmAsm
#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include "abort-macro.S"
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/*
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* Function: v6_early_abort
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*
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* Params : r2 = address of aborted instruction
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* : r3 = saved SPSR
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*
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r2-r8 = corrupted
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* : r9 = preserved
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* : sp = pointer to registers
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*
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* Purpose : obtain information about current aborted instruction.
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* Note: we read user space. This means we might cause a data
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* abort here if the I-TLB and D-TLB aren't seeing the same
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* picture. Unfortunately, this does happen. We live with it.
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*/
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.align 5
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ENTRY(v6_early_abort)
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#ifdef CONFIG_CPU_V6
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sub r1, sp, #4 @ Get unused stack location
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strex r0, r1, [r1] @ Clear the exclusive monitor
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#elif defined(CONFIG_CPU_32v6K)
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clrex
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#endif
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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/*
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* Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
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* The test below covers all the write situations, including Java bytecodes
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*/
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bic r1, r1, #1 << 11 @ clear bit 11 of FSR
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tst r3, #PSR_J_BIT @ Java?
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movne pc, lr
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do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
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ldreq r3, [r2] @ read aborted ARM instruction
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#ifdef CONFIG_CPU_ENDIAN_BE8
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reveq r3, r3
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#endif
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do_ldrd_abort tmp=r2, insn=r3
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tst r3, #1 << 20 @ L = 0 -> write
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orreq r1, r1, #1 << 11 @ yes.
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mov pc, lr
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