182 lines
3.9 KiB
ArmAsm
182 lines
3.9 KiB
ArmAsm
/* tsb.S: Sparc64 TSB table handling.
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*
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* Copyright (C) 2006 David S. Miller <davem@davemloft.net>
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*/
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#include <asm/tsb.h>
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.text
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.align 32
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/* Invoked from TLB miss handler, we are in the
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* MMU global registers and they are setup like
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* this:
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*
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* %g1: TSB entry pointer
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* %g2: available temporary
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* %g3: FAULT_CODE_{D,I}TLB
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* %g4: available temporary
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* %g5: available temporary
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* %g6: TAG TARGET
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* %g7: physical address base of the linux page
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* tables for the current address space
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*/
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.globl tsb_miss_dtlb
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tsb_miss_dtlb:
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g4
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ba,pt %xcc, tsb_miss_page_table_walk
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nop
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.globl tsb_miss_itlb
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tsb_miss_itlb:
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_IMMU, %g4
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ba,pt %xcc, tsb_miss_page_table_walk
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nop
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tsb_miss_page_table_walk:
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/* This clobbers %g1 and %g6, preserve them... */
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mov %g1, %g5
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mov %g6, %g2
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TRAP_LOAD_PGD_PHYS
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mov %g2, %g6
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mov %g5, %g1
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USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
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tsb_reload:
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TSB_LOCK_TAG(%g1, %g2, %g4)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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brgez,a,pn %g5, tsb_do_fault
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stx %g0, [%g1]
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/* If it is larger than the base page size, don't
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* bother putting it into the TSB.
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*/
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srlx %g5, 32, %g2
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sethi %hi(_PAGE_ALL_SZ_BITS >> 32), %g4
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sethi %hi(_PAGE_SZBITS >> 32), %g7
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and %g2, %g4, %g2
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cmp %g2, %g7
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bne,a,pn %xcc, tsb_tlb_reload
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stx %g0, [%g1]
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TSB_WRITE(%g1, %g5, %g6)
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/* Finally, load TLB and return from trap. */
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tsb_tlb_reload:
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cmp %g3, FAULT_CODE_DTLB
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bne,pn %xcc, tsb_itlb_load
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nop
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tsb_dtlb_load:
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stxa %g5, [%g0] ASI_DTLB_DATA_IN
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retry
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tsb_itlb_load:
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stxa %g5, [%g0] ASI_ITLB_DATA_IN
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retry
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/* No valid entry in the page tables, do full fault
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* processing.
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*/
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.globl tsb_do_fault
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tsb_do_fault:
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cmp %g3, FAULT_CODE_DTLB
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rdpr %pstate, %g5
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bne,pn %xcc, tsb_do_itlb_fault
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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tsb_do_dtlb_fault:
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rdpr %tl, %g4
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cmp %g4, 1
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g5
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be,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_DTLB, %g4
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ba,pt %xcc, winfix_trampoline
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nop
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tsb_do_itlb_fault:
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rdpr %tpc, %g5
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ba,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_ITLB, %g4
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.globl sparc64_realfault_common
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sparc64_realfault_common:
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stb %g4, [%g6 + TI_FAULT_CODE] ! Save fault code
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stx %g5, [%g6 + TI_FAULT_ADDR] ! Save fault address
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ba,pt %xcc, etrap ! Save trap state
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1: rd %pc, %g7 ! ...
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call do_sparc64_fault ! Call fault handler
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add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
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ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
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nop ! Delay slot (fill me)
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.globl winfix_trampoline
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winfix_trampoline:
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rdpr %tpc, %g3 ! Prepare winfixup TNPC
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or %g3, 0x7c, %g3 ! Compute branch offset
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wrpr %g3, %tnpc ! Write it into TNPC
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done ! Trap return
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/* Reload MMU related context switch state at
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* schedule() time.
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*
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* %o0: page table physical address
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* %o1: TSB register value
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* %o2: TSB virtual address
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* %o3: TSB mapping locked PTE
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*
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* We have to run this whole thing with interrupts
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* disabled so that the current cpu doesn't change
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* due to preemption.
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*/
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.align 32
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.globl __tsb_context_switch
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__tsb_context_switch:
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rdpr %pstate, %o5
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wrpr %o5, PSTATE_IE, %pstate
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ldub [%g6 + TI_CPU], %g1
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sethi %hi(trap_block), %g2
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sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g1
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or %g2, %lo(trap_block), %g2
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add %g2, %g1, %g2
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stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
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mov TSB_REG, %g1
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stxa %o1, [%g1] ASI_DMMU
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membar #Sync
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stxa %o1, [%g1] ASI_IMMU
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membar #Sync
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brz %o2, 9f
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nop
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/* We use entry 61 for this locked entry. This is the spitfire
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* TLB entry number, and luckily cheetah masks the value with
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* 15 ending us up with entry 13 which is what we want in that
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* case too.
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*
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* XXX Interactions with prom_world()...
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*/
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mov TLB_TAG_ACCESS, %g1
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stxa %o2, [%g1] ASI_DMMU
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membar #Sync
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mov (61 << 3), %g1
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stxa %o3, [%g1] ASI_DTLB_DATA_ACCESS
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membar #Sync
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9:
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wrpr %o5, %pstate
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retl
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nop
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