fef1c772fa
This adds the basic support for running on BPA machines. So far, this is only the IBM workstation, and it will not run on others without a little more generalization. It should be possible to configure a kernel for any combination of CONFIG_PPC_BPA with any of the other multiplatform targets. Signed-off-by: Arnd Bergmann <arndb@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
528 lines
19 KiB
C
528 lines
19 KiB
C
#ifndef __ASM_PPC64_PROCESSOR_H
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#define __ASM_PPC64_PROCESSOR_H
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/*
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* Copyright (C) 2001 PPC 64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/stringify.h>
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#ifndef __ASSEMBLY__
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#include <linux/config.h>
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#include <asm/atomic.h>
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#include <asm/ppcdebug.h>
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#include <asm/a.out.h>
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#endif
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#include <asm/ptrace.h>
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#include <asm/types.h>
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#include <asm/systemcfg.h>
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/* Machine State Register (MSR) Fields */
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#define MSR_SF_LG 63 /* Enable 64 bit mode */
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#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
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#define MSR_HV_LG 60 /* Hypervisor state */
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#define MSR_VEC_LG 25 /* Enable AltiVec */
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#define MSR_POW_LG 18 /* Enable Power Management */
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#define MSR_WE_LG 18 /* Wait State Enable */
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#define MSR_TGPR_LG 17 /* TLB Update registers in use */
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#define MSR_CE_LG 17 /* Critical Interrupt Enable */
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#define MSR_ILE_LG 16 /* Interrupt Little Endian */
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#define MSR_EE_LG 15 /* External Interrupt Enable */
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#define MSR_PR_LG 14 /* Problem State / Privilege Level */
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#define MSR_FP_LG 13 /* Floating Point enable */
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#define MSR_ME_LG 12 /* Machine Check Enable */
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#define MSR_FE0_LG 11 /* Floating Exception mode 0 */
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#define MSR_SE_LG 10 /* Single Step */
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#define MSR_BE_LG 9 /* Branch Trace */
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#define MSR_DE_LG 9 /* Debug Exception Enable */
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#define MSR_FE1_LG 8 /* Floating Exception mode 1 */
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#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
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#define MSR_IR_LG 5 /* Instruction Relocate */
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#define MSR_DR_LG 4 /* Data Relocate */
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#define MSR_PE_LG 3 /* Protection Enable */
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#define MSR_PX_LG 2 /* Protection Exclusive Mode */
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#define MSR_PMM_LG 2 /* Performance monitor */
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#define MSR_RI_LG 1 /* Recoverable Exception */
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#define MSR_LE_LG 0 /* Little Endian */
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#ifdef __ASSEMBLY__
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#define __MASK(X) (1<<(X))
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#else
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#define __MASK(X) (1UL<<(X))
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#endif
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#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
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#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
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#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
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#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
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#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
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#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
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#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
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#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
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#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
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#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
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#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
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#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
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#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
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#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
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#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
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#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
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#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
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#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
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#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
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#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
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#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
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#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
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#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
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#define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
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#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
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#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
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#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF
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#define MSR_KERNEL MSR_ | MSR_SF | MSR_HV
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#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
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#define MSR_USER64 MSR_USER32 | MSR_SF
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/* Floating Point Status and Control Register (FPSCR) Fields */
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#define FPSCR_FX 0x80000000 /* FPU exception summary */
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#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
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#define FPSCR_VX 0x20000000 /* Invalid operation summary */
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#define FPSCR_OX 0x10000000 /* Overflow exception summary */
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#define FPSCR_UX 0x08000000 /* Underflow exception summary */
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#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
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#define FPSCR_XX 0x02000000 /* Inexact exception summary */
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#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
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#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
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#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
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#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
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#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
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#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
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#define FPSCR_FR 0x00040000 /* Fraction rounded */
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#define FPSCR_FI 0x00020000 /* Fraction inexact */
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#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
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#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
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#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
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#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
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#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
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#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
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#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
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#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
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#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
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#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
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#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
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#define FPSCR_RN 0x00000003 /* FPU rounding control */
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/* Special Purpose Registers (SPRNs)*/
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#define SPRN_CTR 0x009 /* Count Register */
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#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
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#define DABR_TRANSLATION (1UL << 2)
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#define SPRN_DAR 0x013 /* Data Address Register */
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#define SPRN_DEC 0x016 /* Decrement Register */
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#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
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#define DSISR_NOHPTE 0x40000000 /* no translation found */
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#define DSISR_PROTFAULT 0x08000000 /* protection fault */
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#define DSISR_ISSTORE 0x02000000 /* access was a store */
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#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
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#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */
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#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
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#define SPRN_MSRDORM 0x3F1 /* Hardware Implementation Register 1 */
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#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
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#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
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#define SPRN_NIADORM 0x3F3 /* Hardware Implementation Register 2 */
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#define SPRN_HID4 0x3F4 /* 970 HID4 */
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#define SPRN_HID5 0x3F6 /* 970 HID5 */
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#define SPRN_HID6 0x3F9 /* BE HID 6 */
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#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
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#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
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#define SPRN_TSCR 0x399 /* Thread switch control on BE */
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#define SPRN_TTR 0x39A /* Thread switch timeout on BE */
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#define TSCR_DEC_ENABLE 0x200000 /* Decrementer Interrupt */
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#define TSCR_EE_ENABLE 0x100000 /* External Interrupt */
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#define TSCR_EE_BOOST 0x080000 /* External Interrupt Boost */
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#define SPRN_TSC 0x3FD /* Thread switch control on others */
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#define SPRN_TST 0x3FC /* Thread switch timeout on others */
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#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
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#define SPRN_LR 0x008 /* Link Register */
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#define SPRN_PIR 0x3FF /* Processor Identification Register */
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#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
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#define SPRN_PURR 0x135 /* Processor Utilization of Resources Register */
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#define SPRN_PVR 0x11F /* Processor Version Register */
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#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
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#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
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#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
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#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
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#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
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#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
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#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
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#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
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#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
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#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
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#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
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#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
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#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, W/O) */
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#define SPRN_TBWU 0x11D /* Time Base Write Upper Register (super, W/O) */
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#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
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#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
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#define SPRN_XER 0x001 /* Fixed Point Exception Register */
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#define SPRN_VRSAVE 0x100 /* Vector save */
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#define SPRN_CTRLF 0x088
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#define SPRN_CTRLT 0x098
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#define CTRL_RUNLATCH 0x1
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/* Performance monitor SPRs */
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#define SPRN_SIAR 780
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#define SPRN_SDAR 781
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#define SPRN_MMCRA 786
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#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
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#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
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#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
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#define SPRN_PMC1 787
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#define SPRN_PMC2 788
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#define SPRN_PMC3 789
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#define SPRN_PMC4 790
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#define SPRN_PMC5 791
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#define SPRN_PMC6 792
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#define SPRN_PMC7 793
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#define SPRN_PMC8 794
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#define SPRN_MMCR0 795
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#define MMCR0_FC 0x80000000UL /* freeze counters. set to 1 on a perfmon exception */
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#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
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#define MMCR0_KERNEL_DISABLE MMCR0_FCS
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#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
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#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
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#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
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#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
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#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
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#define MMCR0_FCECE 0x02000000UL /* freeze counters on enabled condition or event */
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/* time base exception enable */
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#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
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#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
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#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
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#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
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#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
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#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
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#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
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#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
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#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
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#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
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#define SPRN_MMCR1 798
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/* Short-hand versions for a number of the above SPRNs */
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#define CTR SPRN_CTR /* Counter Register */
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#define DAR SPRN_DAR /* Data Address Register */
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#define DABR SPRN_DABR /* Data Address Breakpoint Register */
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#define DEC SPRN_DEC /* Decrement Register */
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#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
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#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
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#define MSRDORM SPRN_MSRDORM /* MSR Dormant Register */
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#define NIADORM SPRN_NIADORM /* NIA Dormant Register */
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#define TSC SPRN_TSC /* Thread switch control */
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#define TST SPRN_TST /* Thread switch timeout */
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#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
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#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
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#define __LR SPRN_LR
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#define PVR SPRN_PVR /* Processor Version */
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#define PIR SPRN_PIR /* Processor ID */
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#define PURR SPRN_PURR /* Processor Utilization of Resource Register */
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#define SDR1 SPRN_SDR1 /* MMU hash base register */
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#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
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#define SPR1 SPRN_SPRG1
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#define SPR2 SPRN_SPRG2
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#define SPR3 SPRN_SPRG3
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#define SPRG0 SPRN_SPRG0
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#define SPRG1 SPRN_SPRG1
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#define SPRG2 SPRN_SPRG2
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#define SPRG3 SPRN_SPRG3
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#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
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#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
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#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
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#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
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#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
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#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
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#define XER SPRN_XER
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/* Processor Version Register (PVR) field extraction */
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#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
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#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
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/* Processor Version Numbers */
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#define PV_NORTHSTAR 0x0033
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#define PV_PULSAR 0x0034
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#define PV_POWER4 0x0035
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#define PV_ICESTAR 0x0036
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#define PV_SSTAR 0x0037
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#define PV_POWER4p 0x0038
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#define PV_970 0x0039
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#define PV_POWER5 0x003A
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#define PV_POWER5p 0x003B
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#define PV_970FX 0x003C
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#define PV_630 0x0040
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#define PV_630p 0x0041
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#define PV_BE 0x0070
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/* Platforms supported by PPC64 */
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#define PLATFORM_PSERIES 0x0100
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#define PLATFORM_PSERIES_LPAR 0x0101
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#define PLATFORM_ISERIES_LPAR 0x0201
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#define PLATFORM_LPAR 0x0001
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#define PLATFORM_POWERMAC 0x0400
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#define PLATFORM_MAPLE 0x0500
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#define PLATFORM_BPA 0x1000
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/* Compatibility with drivers coming from PPC32 world */
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#define _machine (systemcfg->platform)
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#define _MACH_Pmac PLATFORM_POWERMAC
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/*
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* List of interrupt controllers.
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*/
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#define IC_INVALID 0
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#define IC_OPEN_PIC 1
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#define IC_PPC_XIC 2
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#define IC_BPA_IIC 3
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#define XGLUE(a,b) a##b
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#define GLUE(a,b) XGLUE(a,b)
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#ifdef __ASSEMBLY__
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#define _GLOBAL(name) \
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.section ".text"; \
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.align 2 ; \
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.globl name; \
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.globl GLUE(.,name); \
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.section ".opd","aw"; \
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name: \
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.quad GLUE(.,name); \
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.quad .TOC.@tocbase; \
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.quad 0; \
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.previous; \
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.type GLUE(.,name),@function; \
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GLUE(.,name):
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#define _STATIC(name) \
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.section ".text"; \
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.align 2 ; \
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.section ".opd","aw"; \
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name: \
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.quad GLUE(.,name); \
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.quad .TOC.@tocbase; \
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.quad 0; \
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.previous; \
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.type GLUE(.,name),@function; \
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GLUE(.,name):
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#else /* __ASSEMBLY__ */
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ __label__ _l; _l: &&_l;})
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/* Macros for setting and retrieving special purpose registers */
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#define mfmsr() ({unsigned long rval; \
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asm volatile("mfmsr %0" : "=r" (rval)); rval;})
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#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
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: : "r" (v))
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#define mtmsrd(v) __mtmsrd((v), 0)
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#define mfspr(rn) ({unsigned long rval; \
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asm volatile("mfspr %0," __stringify(rn) \
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: "=r" (rval)); rval;})
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#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
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#define mftb() ({unsigned long rval; \
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asm volatile("mftb %0" : "=r" (rval)); rval;})
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#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
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#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
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#define mfasr() ({unsigned long rval; \
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asm volatile("mfasr %0" : "=r" (rval)); rval;})
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static inline void set_tb(unsigned int upper, unsigned int lower)
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{
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mttbl(0);
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mttbu(upper);
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mttbl(lower);
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}
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#define __get_SP() ({unsigned long sp; \
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asm volatile("mr %0,1": "=r" (sp)); sp;})
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#ifdef __KERNEL__
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extern int have_of;
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extern u64 ppc64_interrupt_controller;
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struct task_struct;
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void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
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void release_thread(struct task_struct *);
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/* Prepare to copy thread state - unlazy all lazy status */
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extern void prepare_to_copy(struct task_struct *tsk);
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/* Create a new kernel thread. */
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extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
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/* Lazy FPU handling on uni-processor */
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extern struct task_struct *last_task_used_math;
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extern struct task_struct *last_task_used_altivec;
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/* 64-bit user address space is 41-bits (2TBs user VM) */
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#define TASK_SIZE_USER64 (0x0000020000000000UL)
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/*
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* 32-bit user address space is 4GB - 1 page
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* (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
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*/
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#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
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#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
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TASK_SIZE_USER32 : TASK_SIZE_USER64)
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/* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
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#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
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#define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)||(ppcdebugset(PPCDBG_BINFMT_32ADDR))) ? \
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TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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struct thread_struct {
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unsigned long ksp; /* Kernel stack pointer */
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unsigned long ksp_vsid;
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struct pt_regs *regs; /* Pointer to saved register state */
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mm_segment_t fs; /* for get_fs() validation */
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double fpr[32]; /* Complete floating point set */
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unsigned long fpscr; /* Floating point status (plus pad) */
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unsigned long fpexc_mode; /* Floating-point exception mode */
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unsigned long start_tb; /* Start purr when proc switched in */
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unsigned long accum_tb; /* Total accumilated purr for process */
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unsigned long vdso_base; /* base of the vDSO library */
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#ifdef CONFIG_ALTIVEC
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/* Complete AltiVec register set */
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vector128 vr[32] __attribute((aligned(16)));
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/* AltiVec status */
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vector128 vscr __attribute((aligned(16)));
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unsigned long vrsave;
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int used_vr; /* set if process has used altivec */
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#endif /* CONFIG_ALTIVEC */
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};
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#define ARCH_MIN_TASKALIGN 16
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#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
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#define INIT_THREAD { \
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.ksp = INIT_SP, \
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.regs = (struct pt_regs *)INIT_SP - 1, \
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.fs = KERNEL_DS, \
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.fpr = {0}, \
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.fpscr = 0, \
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.fpexc_mode = MSR_FE0|MSR_FE1, \
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}
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/*
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* Return saved PC of a blocked thread. For now, this is the "user" PC
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*/
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#define thread_saved_pc(tsk) \
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((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
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unsigned long get_wchan(struct task_struct *p);
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#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
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#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
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/* Get/set floating-point exception mode */
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#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
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#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
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extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
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extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
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static inline unsigned int __unpack_fe01(unsigned long msr_bits)
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{
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return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
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}
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static inline unsigned long __pack_fe01(unsigned int fpmode)
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{
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return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
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}
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#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
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/*
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* Prefetch macros.
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*/
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#define ARCH_HAS_PREFETCH
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#define ARCH_HAS_PREFETCHW
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#define ARCH_HAS_SPINLOCK_PREFETCH
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static inline void prefetch(const void *x)
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{
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if (unlikely(!x))
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return;
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__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
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}
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static inline void prefetchw(const void *x)
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{
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if (unlikely(!x))
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return;
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__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
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}
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#define spin_lock_prefetch(x) prefetchw(x)
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#define HAVE_ARCH_PICK_MMAP_LAYOUT
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static inline void ppc64_runlatch_on(void)
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{
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unsigned long ctrl;
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ctrl = mfspr(SPRN_CTRLF);
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ctrl |= CTRL_RUNLATCH;
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mtspr(SPRN_CTRLT, ctrl);
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}
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static inline void ppc64_runlatch_off(void)
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{
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unsigned long ctrl;
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ctrl = mfspr(SPRN_CTRLF);
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ctrl &= ~CTRL_RUNLATCH;
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mtspr(SPRN_CTRLT, ctrl);
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}
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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/*
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* Number of entries in the SLB. If this ever changes we should handle
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* it with a use a cpu feature fixup.
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*/
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#define SLB_NUM_ENTRIES 64
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#endif /* __ASM_PPC64_PROCESSOR_H */
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