2507bc1338
The current debug trap handling code does a number of things that are illegal according to the AVR32 Architecture manual. Most importantly, it may try to schedule from Debug Mode, thus clearing the D bit, which can lead to "undefined behaviour". It seems like this works in most cases, but several people have observed somewhat unstable behaviour when debugging programs, including soft lockups. So there's definitely something which is not right with the existing code. The new code will never schedule from Debug mode, it will always exit Debug mode with a "retd" instruction, and if something not running in Debug mode needs to do something debug-related (like doing a single step), it will enter debug mode through a "breakpoint" instruction. The monitor code will then return directly to user space, bypassing its own saved registers if necessary (since we don't actually care about the trapped context, only the one that came before.) This adds three instructions to the common exception handling code, including one branch. It does not touch super-hot paths like the TLB miss handler. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
159 lines
3.7 KiB
C
159 lines
3.7 KiB
C
/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_AVR32_PROCESSOR_H
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#define __ASM_AVR32_PROCESSOR_H
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#include <asm/page.h>
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#include <asm/cache.h>
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#define TASK_SIZE 0x80000000
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#ifndef __ASSEMBLY__
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static inline void *current_text_addr(void)
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{
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register void *pc asm("pc");
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return pc;
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}
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enum arch_type {
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ARCH_AVR32A,
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ARCH_AVR32B,
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ARCH_MAX
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};
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enum cpu_type {
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CPU_MORGAN,
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CPU_AT32AP,
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CPU_MAX
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};
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enum tlb_config {
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TLB_NONE,
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TLB_SPLIT,
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TLB_UNIFIED,
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TLB_INVALID
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};
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#define AVR32_FEATURE_RMW (1 << 0)
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#define AVR32_FEATURE_DSP (1 << 1)
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#define AVR32_FEATURE_SIMD (1 << 2)
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#define AVR32_FEATURE_OCD (1 << 3)
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#define AVR32_FEATURE_PCTR (1 << 4)
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#define AVR32_FEATURE_JAVA (1 << 5)
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#define AVR32_FEATURE_FPU (1 << 6)
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struct avr32_cpuinfo {
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struct clk *clk;
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unsigned long loops_per_jiffy;
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enum arch_type arch_type;
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enum cpu_type cpu_type;
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unsigned short arch_revision;
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unsigned short cpu_revision;
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enum tlb_config tlb_config;
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unsigned long features;
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struct cache_info icache;
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struct cache_info dcache;
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};
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extern struct avr32_cpuinfo boot_cpu_data;
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#ifdef CONFIG_SMP
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extern struct avr32_cpuinfo cpu_data[];
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#define current_cpu_data cpu_data[smp_processor_id()]
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#else
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#define cpu_data (&boot_cpu_data)
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#define current_cpu_data boot_cpu_data
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#endif
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/* This decides where the kernel will search for a free chunk of vm
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* space during mmap's
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*/
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#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
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#define cpu_relax() barrier()
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#define cpu_sync_pipeline() asm volatile("sub pc, -2" : : : "memory")
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struct cpu_context {
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unsigned long sr;
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unsigned long pc;
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unsigned long ksp; /* Kernel stack pointer */
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unsigned long r7;
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unsigned long r6;
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unsigned long r5;
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unsigned long r4;
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unsigned long r3;
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unsigned long r2;
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unsigned long r1;
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unsigned long r0;
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};
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/* This struct contains the CPU context as stored by switch_to() */
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struct thread_struct {
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struct cpu_context cpu_context;
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unsigned long single_step_addr;
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u16 single_step_insn;
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};
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#define INIT_THREAD { \
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.cpu_context = { \
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.ksp = sizeof(init_stack) + (long)&init_stack, \
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}, \
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}
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/*
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* Do necessary setup to start up a newly executed thread.
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*/
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#define start_thread(regs, new_pc, new_sp) \
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do { \
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set_fs(USER_DS); \
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memset(regs, 0, sizeof(*regs)); \
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regs->sr = MODE_USER; \
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regs->pc = new_pc & ~1; \
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regs->sp = new_sp; \
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} while(0)
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struct task_struct;
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/* Free all resources held by a thread */
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extern void release_thread(struct task_struct *);
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/* Create a kernel thread without removing it from tasklists */
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extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
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/* Prepare to copy thread state - unlazy all lazy status */
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#define prepare_to_copy(tsk) do { } while(0)
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/* Return saved PC of a blocked thread */
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#define thread_saved_pc(tsk) ((tsk)->thread.cpu_context.pc)
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struct pt_regs;
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extern unsigned long get_wchan(struct task_struct *p);
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extern void show_regs_log_lvl(struct pt_regs *regs, const char *log_lvl);
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extern void show_stack_log_lvl(struct task_struct *tsk, unsigned long sp,
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struct pt_regs *regs, const char *log_lvl);
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#define task_pt_regs(p) \
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((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
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#define KSTK_EIP(tsk) ((tsk)->thread.cpu_context.pc)
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#define KSTK_ESP(tsk) ((tsk)->thread.cpu_context.ksp)
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#define ARCH_HAS_PREFETCH
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static inline void prefetch(const void *x)
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{
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const char *c = x;
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asm volatile("pref %0" : : "r"(c));
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}
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#define PREFETCH_STRIDE L1_CACHE_BYTES
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_AVR32_PROCESSOR_H */
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