b8c86fc5d8
The SDHCI interface is not PCI specific, yet the Linux driver was intimitely connected to the PCI bus. This patch properly separates the PCI specific portion from the bus independent code. This patch is based on work by Ben Dooks but he did not have time to complete it. Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
247 lines
7.5 KiB
C
247 lines
7.5 KiB
C
/*
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* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
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*
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* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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/*
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* Controller registers
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*/
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#define SDHCI_DMA_ADDRESS 0x00
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#define SDHCI_BLOCK_SIZE 0x04
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#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
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#define SDHCI_BLOCK_COUNT 0x06
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#define SDHCI_ARGUMENT 0x08
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#define SDHCI_TRANSFER_MODE 0x0C
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#define SDHCI_TRNS_DMA 0x01
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#define SDHCI_TRNS_BLK_CNT_EN 0x02
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#define SDHCI_TRNS_ACMD12 0x04
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#define SDHCI_TRNS_READ 0x10
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#define SDHCI_TRNS_MULTI 0x20
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#define SDHCI_COMMAND 0x0E
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#define SDHCI_CMD_RESP_MASK 0x03
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#define SDHCI_CMD_CRC 0x08
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#define SDHCI_CMD_INDEX 0x10
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#define SDHCI_CMD_DATA 0x20
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#define SDHCI_CMD_RESP_NONE 0x00
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#define SDHCI_CMD_RESP_LONG 0x01
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#define SDHCI_CMD_RESP_SHORT 0x02
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#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
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#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
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#define SDHCI_RESPONSE 0x10
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#define SDHCI_BUFFER 0x20
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#define SDHCI_PRESENT_STATE 0x24
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#define SDHCI_CMD_INHIBIT 0x00000001
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#define SDHCI_DATA_INHIBIT 0x00000002
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#define SDHCI_DOING_WRITE 0x00000100
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#define SDHCI_DOING_READ 0x00000200
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#define SDHCI_SPACE_AVAILABLE 0x00000400
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#define SDHCI_DATA_AVAILABLE 0x00000800
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#define SDHCI_CARD_PRESENT 0x00010000
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#define SDHCI_WRITE_PROTECT 0x00080000
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_CTRL_LED 0x01
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#define SDHCI_CTRL_4BITBUS 0x02
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#define SDHCI_CTRL_HISPD 0x04
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#define SDHCI_POWER_CONTROL 0x29
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#define SDHCI_POWER_ON 0x01
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#define SDHCI_POWER_180 0x0A
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#define SDHCI_POWER_300 0x0C
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#define SDHCI_POWER_330 0x0E
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#define SDHCI_BLOCK_GAP_CONTROL 0x2A
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#define SDHCI_WAKE_UP_CONTROL 0x2B
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#define SDHCI_CLOCK_CONTROL 0x2C
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#define SDHCI_DIVIDER_SHIFT 8
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#define SDHCI_CLOCK_CARD_EN 0x0004
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#define SDHCI_CLOCK_INT_STABLE 0x0002
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#define SDHCI_CLOCK_INT_EN 0x0001
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#define SDHCI_TIMEOUT_CONTROL 0x2E
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#define SDHCI_SOFTWARE_RESET 0x2F
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#define SDHCI_RESET_ALL 0x01
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#define SDHCI_RESET_CMD 0x02
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#define SDHCI_RESET_DATA 0x04
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#define SDHCI_INT_STATUS 0x30
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#define SDHCI_INT_ENABLE 0x34
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#define SDHCI_SIGNAL_ENABLE 0x38
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#define SDHCI_INT_RESPONSE 0x00000001
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#define SDHCI_INT_DATA_END 0x00000002
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#define SDHCI_INT_DMA_END 0x00000008
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#define SDHCI_INT_SPACE_AVAIL 0x00000010
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#define SDHCI_INT_DATA_AVAIL 0x00000020
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#define SDHCI_INT_CARD_INSERT 0x00000040
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#define SDHCI_INT_CARD_REMOVE 0x00000080
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#define SDHCI_INT_CARD_INT 0x00000100
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#define SDHCI_INT_ERROR 0x00008000
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#define SDHCI_INT_TIMEOUT 0x00010000
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#define SDHCI_INT_CRC 0x00020000
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#define SDHCI_INT_END_BIT 0x00040000
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#define SDHCI_INT_INDEX 0x00080000
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#define SDHCI_INT_DATA_TIMEOUT 0x00100000
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#define SDHCI_INT_DATA_CRC 0x00200000
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#define SDHCI_INT_DATA_END_BIT 0x00400000
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#define SDHCI_INT_BUS_POWER 0x00800000
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#define SDHCI_INT_ACMD12ERR 0x01000000
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#define SDHCI_INT_NORMAL_MASK 0x00007FFF
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#define SDHCI_INT_ERROR_MASK 0xFFFF8000
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#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
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SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
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#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
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SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
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SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
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SDHCI_INT_DATA_END_BIT)
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#define SDHCI_ACMD12_ERR 0x3C
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/* 3E-3F reserved */
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#define SDHCI_CAPABILITIES 0x40
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#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
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#define SDHCI_TIMEOUT_CLK_SHIFT 0
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#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
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#define SDHCI_CLOCK_BASE_MASK 0x00003F00
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#define SDHCI_CLOCK_BASE_SHIFT 8
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#define SDHCI_MAX_BLOCK_MASK 0x00030000
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#define SDHCI_MAX_BLOCK_SHIFT 16
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#define SDHCI_CAN_DO_HISPD 0x00200000
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#define SDHCI_CAN_DO_DMA 0x00400000
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#define SDHCI_CAN_VDD_330 0x01000000
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#define SDHCI_CAN_VDD_300 0x02000000
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#define SDHCI_CAN_VDD_180 0x04000000
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/* 44-47 reserved for more caps */
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#define SDHCI_MAX_CURRENT 0x48
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/* 4C-4F reserved for more max current */
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/* 50-FB reserved */
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#define SDHCI_SLOT_INT_STATUS 0xFC
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#define SDHCI_HOST_VERSION 0xFE
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#define SDHCI_VENDOR_VER_MASK 0xFF00
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#define SDHCI_VENDOR_VER_SHIFT 8
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#define SDHCI_SPEC_VER_MASK 0x00FF
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#define SDHCI_SPEC_VER_SHIFT 0
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struct sdhci_ops;
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struct sdhci_host {
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/* Data set by hardware interface driver */
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const char *hw_name; /* Hardware bus name */
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unsigned int quirks; /* Deviations from spec. */
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/* Controller doesn't honor resets unless we touch the clock register */
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#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
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/* Controller has bad caps bits, but really supports DMA */
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#define SDHCI_QUIRK_FORCE_DMA (1<<1)
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/* Controller doesn't like to be reset when there is no card inserted. */
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#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
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/* Controller doesn't like clearing the power reg before a change */
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#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
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/* Controller has flaky internal state so reset it on each ios change */
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#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
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/* Controller has an unusable DMA engine */
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#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
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/* Controller can only DMA from 32-bit aligned addresses */
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#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6)
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/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
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#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7)
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/* Controller needs to be reset after each request to stay stable */
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#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8)
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/* Controller needs voltage and power writes to happen separately */
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#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<9)
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/* Controller has an off-by-one issue with timeout value */
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#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<10)
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int irq; /* Device IRQ */
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void __iomem * ioaddr; /* Mapped address */
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const struct sdhci_ops *ops; /* Low level hw interface */
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/* Internal data */
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struct mmc_host *mmc; /* MMC structure */
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#ifdef CONFIG_LEDS_CLASS
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struct led_classdev led; /* LED control */
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#endif
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spinlock_t lock; /* Mutex */
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int flags; /* Host attributes */
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#define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */
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#define SDHCI_REQ_USE_DMA (1<<1) /* Use DMA for this req. */
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unsigned int max_clk; /* Max possible freq (MHz) */
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unsigned int timeout_clk; /* Timeout freq (KHz) */
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unsigned int clock; /* Current clock (MHz) */
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unsigned short power; /* Current voltage */
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struct mmc_request *mrq; /* Current request */
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struct mmc_command *cmd; /* Current command */
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struct mmc_data *data; /* Current data request */
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unsigned int data_early:1; /* Data finished before cmd */
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struct scatterlist *cur_sg; /* We're working on this */
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int num_sg; /* Entries left */
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int offset; /* Offset into current sg */
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int remain; /* Bytes left in current */
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struct tasklet_struct card_tasklet; /* Tasklet structures */
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struct tasklet_struct finish_tasklet;
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struct timer_list timer; /* Timer for timeouts */
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unsigned long private[0] ____cacheline_aligned;
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};
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struct sdhci_ops {
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int (*enable_dma)(struct sdhci_host *host);
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};
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extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
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size_t priv_size);
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extern void sdhci_free_host(struct sdhci_host *host);
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static inline void *sdhci_priv(struct sdhci_host *host)
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{
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return (void *)host->private;
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}
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extern int sdhci_add_host(struct sdhci_host *host);
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extern void sdhci_remove_host(struct sdhci_host *host);
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#ifdef CONFIG_PM
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extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
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extern int sdhci_resume_host(struct sdhci_host *host);
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#endif
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