05781ccd74
Various instances of the EMAC core have varying: 1) number of address match slots, 2) width of the registers for handling address match slots, 3) number of registers for handling address match slots and 4) base offset for those registers. As the driver stands today, it assumes that all EMACs have 4 IAHT and GAHT 32-bit registers, starting at offset 0x30 from the register base, with only 16-bits of each used for a total of 64 match slots. The 405EX(r) and 460EX now use the EMAC4SYNC core rather than the EMAC4 core. This core has 8 IAHT and GAHT registers, starting at offset 0x80 from the register base, with ALL 32-bits of each used for a total of 256 match slots. This adds a new compatible device tree entry "emac4sync" and a new, related feature flag "EMAC_FTR_EMAC4SYNC" along with a series of macros and inlines which supply the appropriate parameterized value based on the presence or absence of the EMAC4SYNC feature. The code has further been reworked where appropriate to use those macros and inlines. In addition, the register size passed to ioremap is now taken from the device tree: c4 for EMAC4SYNC cores 74 for EMAC4 cores 70 for EMAC cores rather than sizeof (emac_regs). Finally, the device trees have been updated with the appropriate compatible entries and resource sizes. This has been tested on an AMCC Haleakala board such that: 1) inbound ICMP requests to 'haleakala.local' via MDNS from both Mac OS X 10.4.11 and Ubuntu 8.04 systems as well as 2) outbound ICMP requests from 'haleakala.local' to those same systems in the '.local' domain via MDNS now work. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Acked-by: Jeff Garzik <jgarzik@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
450 lines
11 KiB
C
450 lines
11 KiB
C
/*
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* drivers/net/ibm_newemac/core.h
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*
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* Driver for PowerPC 4xx on-chip ethernet controller.
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*
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* Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
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* <benh@kernel.crashing.org>
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*
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* Based on the arch/ppc version of the driver:
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*
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* Copyright (c) 2004, 2005 Zultys Technologies.
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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*
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* Based on original work by
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* Armin Kuster <akuster@mvista.com>
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* Johnnie Peters <jpeters@mvista.com>
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* Copyright 2000, 2001 MontaVista Softare Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __IBM_NEWEMAC_CORE_H
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#define __IBM_NEWEMAC_CORE_H
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/netdevice.h>
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#include <linux/dma-mapping.h>
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#include <linux/spinlock.h>
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#include <linux/of_platform.h>
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#include <asm/io.h>
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#include <asm/dcr.h>
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#include "emac.h"
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#include "phy.h"
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#include "zmii.h"
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#include "rgmii.h"
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#include "mal.h"
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#include "tah.h"
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#include "debug.h"
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#define NUM_TX_BUFF CONFIG_IBM_NEW_EMAC_TXB
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#define NUM_RX_BUFF CONFIG_IBM_NEW_EMAC_RXB
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/* Simple sanity check */
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#if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
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#error Invalid number of buffer descriptors (greater than 256)
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#endif
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#define EMAC_MIN_MTU 46
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/* Maximum L2 header length (VLAN tagged, no FCS) */
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#define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4)
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/* RX BD size for the given MTU */
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static inline int emac_rx_size(int mtu)
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{
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if (mtu > ETH_DATA_LEN)
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return MAL_MAX_RX_SIZE;
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else
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return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
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}
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#define EMAC_DMA_ALIGN(x) ALIGN((x), dma_get_cache_alignment())
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#define EMAC_RX_SKB_HEADROOM \
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EMAC_DMA_ALIGN(CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM)
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/* Size of RX skb for the given MTU */
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static inline int emac_rx_skb_size(int mtu)
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{
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int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
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return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM;
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}
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/* RX DMA sync size */
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static inline int emac_rx_sync_size(int mtu)
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{
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return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2);
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}
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/* Driver statistcs is split into two parts to make it more cache friendly:
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* - normal statistics (packet count, etc)
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* - error statistics
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*
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* When statistics is requested by ethtool, these parts are concatenated,
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* normal one goes first.
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*
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* Please, keep these structures in sync with emac_stats_keys.
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*/
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/* Normal TX/RX Statistics */
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struct emac_stats {
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u64 rx_packets;
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u64 rx_bytes;
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u64 tx_packets;
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u64 tx_bytes;
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u64 rx_packets_csum;
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u64 tx_packets_csum;
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};
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/* Error statistics */
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struct emac_error_stats {
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u64 tx_undo;
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/* Software RX Errors */
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u64 rx_dropped_stack;
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u64 rx_dropped_oom;
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u64 rx_dropped_error;
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u64 rx_dropped_resize;
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u64 rx_dropped_mtu;
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u64 rx_stopped;
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/* BD reported RX errors */
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u64 rx_bd_errors;
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u64 rx_bd_overrun;
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u64 rx_bd_bad_packet;
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u64 rx_bd_runt_packet;
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u64 rx_bd_short_event;
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u64 rx_bd_alignment_error;
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u64 rx_bd_bad_fcs;
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u64 rx_bd_packet_too_long;
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u64 rx_bd_out_of_range;
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u64 rx_bd_in_range;
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/* EMAC IRQ reported RX errors */
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u64 rx_parity;
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u64 rx_fifo_overrun;
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u64 rx_overrun;
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u64 rx_bad_packet;
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u64 rx_runt_packet;
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u64 rx_short_event;
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u64 rx_alignment_error;
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u64 rx_bad_fcs;
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u64 rx_packet_too_long;
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u64 rx_out_of_range;
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u64 rx_in_range;
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/* Software TX Errors */
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u64 tx_dropped;
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/* BD reported TX errors */
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u64 tx_bd_errors;
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u64 tx_bd_bad_fcs;
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u64 tx_bd_carrier_loss;
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u64 tx_bd_excessive_deferral;
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u64 tx_bd_excessive_collisions;
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u64 tx_bd_late_collision;
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u64 tx_bd_multple_collisions;
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u64 tx_bd_single_collision;
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u64 tx_bd_underrun;
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u64 tx_bd_sqe;
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/* EMAC IRQ reported TX errors */
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u64 tx_parity;
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u64 tx_underrun;
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u64 tx_sqe;
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u64 tx_errors;
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};
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#define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct emac_stats) + \
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sizeof(struct emac_error_stats)) \
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/ sizeof(u64))
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struct emac_instance {
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struct net_device *ndev;
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struct resource rsrc_regs;
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struct emac_regs __iomem *emacp;
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struct of_device *ofdev;
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struct device_node **blist; /* bootlist entry */
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/* MAL linkage */
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u32 mal_ph;
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struct of_device *mal_dev;
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u32 mal_rx_chan;
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u32 mal_tx_chan;
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struct mal_instance *mal;
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struct mal_commac commac;
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/* PHY infos */
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u32 phy_mode;
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u32 phy_map;
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u32 phy_address;
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u32 phy_feat_exc;
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struct mii_phy phy;
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struct mutex link_lock;
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struct delayed_work link_work;
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int link_polling;
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/* Shared MDIO if any */
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u32 mdio_ph;
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struct of_device *mdio_dev;
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struct emac_instance *mdio_instance;
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struct mutex mdio_lock;
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/* ZMII infos if any */
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u32 zmii_ph;
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u32 zmii_port;
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struct of_device *zmii_dev;
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/* RGMII infos if any */
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u32 rgmii_ph;
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u32 rgmii_port;
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struct of_device *rgmii_dev;
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/* TAH infos if any */
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u32 tah_ph;
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u32 tah_port;
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struct of_device *tah_dev;
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/* IRQs */
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int wol_irq;
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int emac_irq;
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/* OPB bus frequency in Mhz */
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u32 opb_bus_freq;
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/* Cell index within an ASIC (for clk mgmnt) */
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u32 cell_index;
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/* Max supported MTU */
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u32 max_mtu;
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/* Feature bits (from probe table) */
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unsigned int features;
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/* Tx and Rx fifo sizes & other infos in bytes */
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u32 tx_fifo_size;
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u32 tx_fifo_size_gige;
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u32 rx_fifo_size;
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u32 rx_fifo_size_gige;
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u32 fifo_entry_size;
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u32 mal_burst_size; /* move to MAL ? */
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/* IAHT and GAHT filter parameterization */
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u32 xaht_slots_shift;
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u32 xaht_width_shift;
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/* Descriptor management
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*/
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struct mal_descriptor *tx_desc;
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int tx_cnt;
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int tx_slot;
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int ack_slot;
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struct mal_descriptor *rx_desc;
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int rx_slot;
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struct sk_buff *rx_sg_skb; /* 1 */
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int rx_skb_size;
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int rx_sync_size;
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struct sk_buff *tx_skb[NUM_TX_BUFF];
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struct sk_buff *rx_skb[NUM_RX_BUFF];
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/* Stats
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*/
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struct emac_error_stats estats;
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struct net_device_stats nstats;
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struct emac_stats stats;
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/* Misc
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*/
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int reset_failed;
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int stop_timeout; /* in us */
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int no_mcast;
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int mcast_pending;
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int opened;
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struct work_struct reset_work;
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spinlock_t lock;
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};
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/*
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* Features of various EMAC implementations
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*/
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/*
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* No flow control on 40x according to the original driver
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*/
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#define EMAC_FTR_NO_FLOW_CONTROL_40x 0x00000001
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/*
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* Cell is an EMAC4
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*/
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#define EMAC_FTR_EMAC4 0x00000002
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/*
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* For the 440SPe, AMCC inexplicably changed the polarity of
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* the "operation complete" bit in the MII control register.
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*/
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#define EMAC_FTR_STACR_OC_INVERT 0x00000004
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/*
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* Set if we have a TAH.
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*/
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#define EMAC_FTR_HAS_TAH 0x00000008
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/*
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* Set if we have a ZMII.
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*/
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#define EMAC_FTR_HAS_ZMII 0x00000010
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/*
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* Set if we have a RGMII.
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*/
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#define EMAC_FTR_HAS_RGMII 0x00000020
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/*
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* Set if we have new type STACR with STAOPC
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*/
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#define EMAC_FTR_HAS_NEW_STACR 0x00000040
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/*
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* Set if we need phy clock workaround for 440gx
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*/
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#define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080
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/*
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* Set if we need phy clock workaround for 440ep or 440gr
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*/
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#define EMAC_FTR_440EP_PHY_CLK_FIX 0x00000100
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/*
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* The 405EX and 460EX contain the EMAC4SYNC core
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*/
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#define EMAC_FTR_EMAC4SYNC 0x00000200
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/* Right now, we don't quite handle the always/possible masks on the
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* most optimal way as we don't have a way to say something like
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* always EMAC4. Patches welcome.
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*/
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enum {
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EMAC_FTRS_ALWAYS = 0,
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EMAC_FTRS_POSSIBLE =
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#ifdef CONFIG_IBM_NEW_EMAC_EMAC4
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EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC |
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EMAC_FTR_HAS_NEW_STACR |
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EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX |
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#endif
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#ifdef CONFIG_IBM_NEW_EMAC_TAH
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EMAC_FTR_HAS_TAH |
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#endif
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#ifdef CONFIG_IBM_NEW_EMAC_ZMII
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EMAC_FTR_HAS_ZMII |
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#endif
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#ifdef CONFIG_IBM_NEW_EMAC_RGMII
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EMAC_FTR_HAS_RGMII |
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#endif
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EMAC_FTR_440EP_PHY_CLK_FIX,
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};
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static inline int emac_has_feature(struct emac_instance *dev,
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unsigned long feature)
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{
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return (EMAC_FTRS_ALWAYS & feature) ||
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(EMAC_FTRS_POSSIBLE & dev->features & feature);
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}
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/*
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* Various instances of the EMAC core have varying 1) number of
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* address match slots, 2) width of the registers for handling address
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* match slots, 3) number of registers for handling address match
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* slots and 4) base offset for those registers.
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*
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* These macros and inlines handle these differences based on
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* parameters supplied by the device structure which are, in turn,
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* initialized based on the "compatible" entry in the device tree.
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*/
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#define EMAC4_XAHT_SLOTS_SHIFT 6
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#define EMAC4_XAHT_WIDTH_SHIFT 4
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#define EMAC4SYNC_XAHT_SLOTS_SHIFT 8
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#define EMAC4SYNC_XAHT_WIDTH_SHIFT 5
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#define EMAC_XAHT_SLOTS(dev) (1 << (dev)->xaht_slots_shift)
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#define EMAC_XAHT_WIDTH(dev) (1 << (dev)->xaht_width_shift)
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#define EMAC_XAHT_REGS(dev) (1 << ((dev)->xaht_slots_shift - \
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(dev)->xaht_width_shift))
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#define EMAC_XAHT_CRC_TO_SLOT(dev, crc) \
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((EMAC_XAHT_SLOTS(dev) - 1) - \
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((crc) >> ((sizeof (u32) * BITS_PER_BYTE) - \
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(dev)->xaht_slots_shift)))
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#define EMAC_XAHT_SLOT_TO_REG(dev, slot) \
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((slot) >> (dev)->xaht_width_shift)
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#define EMAC_XAHT_SLOT_TO_MASK(dev, slot) \
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((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >> \
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((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1)))
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static inline u32 *emac_xaht_base(struct emac_instance *dev)
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{
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struct emac_regs __iomem *p = dev->emacp;
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int offset;
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/* The first IAHT entry always is the base of the block of
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* IAHT and GAHT registers.
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*/
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if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC))
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offset = offsetof(struct emac_regs, u1.emac4sync.iaht1);
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else
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offset = offsetof(struct emac_regs, u0.emac4.iaht1);
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return ((u32 *)((ptrdiff_t)p + offset));
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}
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static inline u32 *emac_gaht_base(struct emac_instance *dev)
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{
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/* GAHT registers always come after an identical number of
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* IAHT registers.
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*/
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return (emac_xaht_base(dev) + EMAC_XAHT_REGS(dev));
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}
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static inline u32 *emac_iaht_base(struct emac_instance *dev)
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{
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/* IAHT registers always come before an identical number of
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* GAHT registers.
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*/
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return (emac_xaht_base(dev));
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}
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/* Ethtool get_regs complex data.
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* We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
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* when available.
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*
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* Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
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* MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
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* Each register component is preceded with emac_ethtool_regs_subhdr.
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* Order of the optional headers follows their relative bit posititions
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* in emac_ethtool_regs_hdr.components
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*/
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#define EMAC_ETHTOOL_REGS_ZMII 0x00000001
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#define EMAC_ETHTOOL_REGS_RGMII 0x00000002
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#define EMAC_ETHTOOL_REGS_TAH 0x00000004
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struct emac_ethtool_regs_hdr {
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u32 components;
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};
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struct emac_ethtool_regs_subhdr {
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u32 version;
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u32 index;
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};
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#define EMAC_ETHTOOL_REGS_VER 0
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#define EMAC_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \
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(dev)->rsrc_regs.start + 1)
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#define EMAC4_ETHTOOL_REGS_VER 1
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#define EMAC4_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \
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(dev)->rsrc_regs.start + 1)
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#endif /* __IBM_NEWEMAC_CORE_H */
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