24420760c3
+m is really correct for a RMW instruction, but some older gccs error out. I finally gave in and ifdefed it. This fixes compilation errors with some compiler version. Signed-off-by: Andi Kleen <ak@suse.de>
427 lines
10 KiB
C
427 lines
10 KiB
C
#ifndef _X86_64_BITOPS_H
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#define _X86_64_BITOPS_H
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/*
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* Copyright 1992, Linus Torvalds.
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*/
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#include <asm/alternative.h>
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#if __GNUC__ < 4 || __GNUC_MINOR__ < 1
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/* Technically wrong, but this avoids compilation errors on some gcc
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versions. */
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#define ADDR "=m" (*(volatile long *) addr)
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#else
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#define ADDR "+m" (*(volatile long *) addr)
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#endif
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static __inline__ void set_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__( LOCK_PREFIX
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"btsl %1,%0"
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:ADDR
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:"dIr" (nr) : "memory");
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}
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/**
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* __set_bit - Set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* Unlike set_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static __inline__ void __set_bit(int nr, volatile void * addr)
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{
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__asm__ volatile(
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"btsl %1,%0"
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:ADDR
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:"dIr" (nr) : "memory");
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static __inline__ void clear_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__( LOCK_PREFIX
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"btrl %1,%0"
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:ADDR
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:"dIr" (nr));
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}
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static __inline__ void __clear_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__(
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"btrl %1,%0"
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:ADDR
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:"dIr" (nr));
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}
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#define smp_mb__before_clear_bit() barrier()
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#define smp_mb__after_clear_bit() barrier()
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/**
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* __change_bit - Toggle a bit in memory
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* @nr: the bit to change
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* @addr: the address to start counting from
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*
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* Unlike change_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static __inline__ void __change_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__(
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"btcl %1,%0"
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:ADDR
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:"dIr" (nr));
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}
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/**
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* change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static __inline__ void change_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__( LOCK_PREFIX
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"btcl %1,%0"
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:ADDR
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:"dIr" (nr));
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}
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int test_and_set_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__ __volatile__( LOCK_PREFIX
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"btsl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),ADDR
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:"dIr" (nr) : "memory");
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return oldbit;
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}
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/**
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* __test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__(
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"btsl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),ADDR
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:"dIr" (nr));
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return oldbit;
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__ __volatile__( LOCK_PREFIX
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"btrl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),ADDR
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:"dIr" (nr) : "memory");
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return oldbit;
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}
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/**
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* __test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__(
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"btrl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),ADDR
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:"dIr" (nr));
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return oldbit;
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}
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/* WARNING: non atomic and it can be reordered! */
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static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__ __volatile__(
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"btcl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),ADDR
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:"dIr" (nr) : "memory");
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return oldbit;
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}
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/**
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int test_and_change_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__ __volatile__( LOCK_PREFIX
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"btcl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),ADDR
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:"dIr" (nr) : "memory");
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return oldbit;
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}
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#if 0 /* Fool kernel-doc since it doesn't do macros yet */
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/**
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* test_bit - Determine whether a bit is set
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* @nr: bit number to test
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* @addr: Address to start counting from
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*/
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static int test_bit(int nr, const volatile void * addr);
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#endif
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static __inline__ int constant_test_bit(int nr, const volatile void * addr)
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{
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return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
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}
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static __inline__ int variable_test_bit(int nr, volatile const void * addr)
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{
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int oldbit;
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__asm__ __volatile__(
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"btl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit)
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:"m" (*(volatile long *)addr),"dIr" (nr));
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return oldbit;
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}
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#define test_bit(nr,addr) \
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(__builtin_constant_p(nr) ? \
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constant_test_bit((nr),(addr)) : \
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variable_test_bit((nr),(addr)))
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#undef ADDR
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extern long find_first_zero_bit(const unsigned long * addr, unsigned long size);
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extern long find_next_zero_bit (const unsigned long * addr, long size, long offset);
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extern long find_first_bit(const unsigned long * addr, unsigned long size);
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extern long find_next_bit(const unsigned long * addr, long size, long offset);
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/* return index of first bet set in val or max when no bit is set */
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static inline unsigned long __scanbit(unsigned long val, unsigned long max)
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{
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asm("bsfq %1,%0 ; cmovz %2,%0" : "=&r" (val) : "r" (val), "r" (max));
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return val;
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}
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#define find_first_bit(addr,size) \
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((__builtin_constant_p(size) && (size) <= BITS_PER_LONG ? \
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(__scanbit(*(unsigned long *)addr,(size))) : \
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find_first_bit(addr,size)))
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#define find_next_bit(addr,size,off) \
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((__builtin_constant_p(size) && (size) <= BITS_PER_LONG ? \
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((off) + (__scanbit((*(unsigned long *)addr) >> (off),(size)-(off)))) : \
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find_next_bit(addr,size,off)))
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#define find_first_zero_bit(addr,size) \
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((__builtin_constant_p(size) && (size) <= BITS_PER_LONG ? \
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(__scanbit(~*(unsigned long *)addr,(size))) : \
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find_first_zero_bit(addr,size)))
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#define find_next_zero_bit(addr,size,off) \
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((__builtin_constant_p(size) && (size) <= BITS_PER_LONG ? \
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((off)+(__scanbit(~(((*(unsigned long *)addr)) >> (off)),(size)-(off)))) : \
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find_next_zero_bit(addr,size,off)))
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/*
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* Find string of zero bits in a bitmap. -1 when not found.
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*/
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extern unsigned long
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find_next_zero_string(unsigned long *bitmap, long start, long nbits, int len);
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static inline void set_bit_string(unsigned long *bitmap, unsigned long i,
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int len)
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{
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unsigned long end = i + len;
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while (i < end) {
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__set_bit(i, bitmap);
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i++;
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}
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}
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static inline void __clear_bit_string(unsigned long *bitmap, unsigned long i,
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int len)
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{
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unsigned long end = i + len;
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while (i < end) {
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__clear_bit(i, bitmap);
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i++;
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}
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}
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/**
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* ffz - find first zero in word.
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* @word: The word to search
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*
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* Undefined if no zero exists, so code should check against ~0UL first.
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*/
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static __inline__ unsigned long ffz(unsigned long word)
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{
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__asm__("bsfq %1,%0"
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:"=r" (word)
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:"r" (~word));
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return word;
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}
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/**
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* __ffs - find first bit in word.
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* @word: The word to search
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*
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* Undefined if no bit exists, so code should check against 0 first.
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*/
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static __inline__ unsigned long __ffs(unsigned long word)
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{
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__asm__("bsfq %1,%0"
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:"=r" (word)
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:"rm" (word));
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return word;
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}
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/*
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* __fls: find last bit set.
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* @word: The word to search
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*
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* Undefined if no zero exists, so code should check against ~0UL first.
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*/
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static __inline__ unsigned long __fls(unsigned long word)
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{
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__asm__("bsrq %1,%0"
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:"=r" (word)
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:"rm" (word));
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return word;
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}
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#ifdef __KERNEL__
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#include <asm-generic/bitops/sched.h>
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/**
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* ffs - find first bit set
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* @x: the word to search
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*
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* This is defined the same way as
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* the libc and compiler builtin ffs routines, therefore
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* differs in spirit from the above ffz (man ffs).
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*/
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static __inline__ int ffs(int x)
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{
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int r;
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__asm__("bsfl %1,%0\n\t"
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"cmovzl %2,%0"
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: "=r" (r) : "rm" (x), "r" (-1));
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return r+1;
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}
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/**
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* fls64 - find last bit set in 64 bit word
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* @x: the word to search
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*
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* This is defined the same way as fls.
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*/
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static __inline__ int fls64(__u64 x)
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{
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if (x == 0)
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return 0;
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return __fls(x) + 1;
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}
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/**
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* fls - find last bit set
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* @x: the word to search
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*
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* This is defined the same way as ffs.
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*/
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static __inline__ int fls(int x)
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{
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int r;
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__asm__("bsrl %1,%0\n\t"
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"cmovzl %2,%0"
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: "=&r" (r) : "rm" (x), "rm" (-1));
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return r+1;
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}
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#define ARCH_HAS_FAST_MULTIPLIER 1
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#include <asm-generic/bitops/hweight.h>
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#endif /* __KERNEL__ */
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#ifdef __KERNEL__
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#include <asm-generic/bitops/ext2-non-atomic.h>
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#define ext2_set_bit_atomic(lock,nr,addr) \
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test_and_set_bit((nr),(unsigned long*)addr)
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#define ext2_clear_bit_atomic(lock,nr,addr) \
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test_and_clear_bit((nr),(unsigned long*)addr)
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#include <asm-generic/bitops/minix.h>
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#endif /* __KERNEL__ */
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#endif /* _X86_64_BITOPS_H */
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