30343ef1de
Allow the crypto engines to be matched from device tree bindings. Cc: devicetree-discuss@lists.ozlabs.org Cc: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
23 lines
789 B
Text
23 lines
789 B
Text
Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
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Picochip picoXcell devices contain crypto offload engines that may be used for
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IPSEC and femtocell layer 2 ciphering.
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Required properties:
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- compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
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"picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
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- reg : Offset and length of the register set for this device
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- interrupt-parent : The interrupt controller that controls the SPAcc
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interrupt.
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- interrupts : The interrupt line from the SPAcc.
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- ref-clock : The input clock that drives the SPAcc.
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Example SPAcc node:
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spacc@10000 {
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compatible = "picochip,spacc-ipsec";
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reg = <0x100000 0x10000>;
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interrupt-parent = <&vic0>;
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interrupts = <24>;
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ref-clock = <&ipsec_clk>, "ref";
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};
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