b238e90e99
The TSF has to be reset only once, upon bringing the interface up in AP mode. For any beacon reconfigure calls after that, resetting the TSF results in incorrect beacon generation. The only exception is a change in the beacon interval, which is indicated to the driver by mac80211 through IEEE80211_CONF_CHANGE_BEACON_INTERVAL, handle this properly. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
686 lines
19 KiB
C
686 lines
19 KiB
C
/*
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* Copyright (c) 2008 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef ATH9K_H
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#define ATH9K_H
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#include <linux/etherdevice.h>
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#include <linux/device.h>
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#include <net/mac80211.h>
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#include <linux/leds.h>
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#include <linux/rfkill.h>
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#include "hw.h"
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#include "rc.h"
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#include "debug.h"
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struct ath_node;
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/* Macro to expand scalars to 64-bit objects */
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#define ito64(x) (sizeof(x) == 8) ? \
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(((unsigned long long int)(x)) & (0xff)) : \
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(sizeof(x) == 16) ? \
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(((unsigned long long int)(x)) & 0xffff) : \
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((sizeof(x) == 32) ? \
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(((unsigned long long int)(x)) & 0xffffffff) : \
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(unsigned long long int)(x))
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/* increment with wrap-around */
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#define INCR(_l, _sz) do { \
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(_l)++; \
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(_l) &= ((_sz) - 1); \
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} while (0)
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/* decrement with wrap-around */
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#define DECR(_l, _sz) do { \
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(_l)--; \
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(_l) &= ((_sz) - 1); \
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} while (0)
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#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
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#define ASSERT(exp) do { \
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if (unlikely(!(exp))) { \
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BUG(); \
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} \
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} while (0)
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#define TSF_TO_TU(_h,_l) \
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((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
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#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
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static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
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struct ath_config {
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u32 ath_aggr_prot;
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u16 txpowlimit;
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u8 cabqReadytime;
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u8 swBeaconProcess;
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};
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/*************************/
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/* Descriptor Management */
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/*************************/
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#define ATH_TXBUF_RESET(_bf) do { \
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(_bf)->bf_status = 0; \
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(_bf)->bf_lastbf = NULL; \
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(_bf)->bf_next = NULL; \
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memset(&((_bf)->bf_state), 0, \
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sizeof(struct ath_buf_state)); \
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} while (0)
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/**
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* enum buffer_type - Buffer type flags
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*
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* @BUF_HT: Send this buffer using HT capabilities
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* @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
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* @BUF_AGGR: Indicates whether the buffer can be aggregated
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* (used in aggregation scheduling)
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* @BUF_RETRY: Indicates whether the buffer is retried
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* @BUF_XRETRY: To denote excessive retries of the buffer
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*/
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enum buffer_type {
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BUF_HT = BIT(1),
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BUF_AMPDU = BIT(2),
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BUF_AGGR = BIT(3),
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BUF_RETRY = BIT(4),
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BUF_XRETRY = BIT(5),
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};
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struct ath_buf_state {
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int bfs_nframes;
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u16 bfs_al;
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u16 bfs_frmlen;
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int bfs_seqno;
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int bfs_tidno;
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int bfs_retries;
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u32 bf_type;
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u32 bfs_keyix;
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enum ath9k_key_type bfs_keytype;
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};
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#define bf_nframes bf_state.bfs_nframes
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#define bf_al bf_state.bfs_al
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#define bf_frmlen bf_state.bfs_frmlen
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#define bf_retries bf_state.bfs_retries
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#define bf_seqno bf_state.bfs_seqno
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#define bf_tidno bf_state.bfs_tidno
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#define bf_keyix bf_state.bfs_keyix
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#define bf_keytype bf_state.bfs_keytype
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#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
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#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
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#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
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#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
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#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
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struct ath_buf {
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struct list_head list;
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struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
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an aggregate) */
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struct ath_buf *bf_next; /* next subframe in the aggregate */
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void *bf_mpdu; /* enclosing frame structure */
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struct ath_desc *bf_desc; /* virtual addr of desc */
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dma_addr_t bf_daddr; /* physical addr of desc */
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dma_addr_t bf_buf_addr; /* physical addr of data buffer */
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u32 bf_status;
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u16 bf_flags;
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struct ath_buf_state bf_state;
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dma_addr_t bf_dmacontext;
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};
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#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
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#define ATH_BUFSTATUS_STALE 0x00000002
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struct ath_descdma {
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const char *dd_name;
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struct ath_desc *dd_desc;
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dma_addr_t dd_desc_paddr;
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u32 dd_desc_len;
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struct ath_buf *dd_bufptr;
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dma_addr_t dd_dmacontext;
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};
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int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
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struct list_head *head, const char *name,
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int nbuf, int ndesc);
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void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
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struct list_head *head);
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/***********/
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/* RX / TX */
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/***********/
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#define ATH_MAX_ANTENNA 3
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#define ATH_RXBUF 512
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#define WME_NUM_TID 16
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#define ATH_TXBUF 512
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#define ATH_TXMAXTRY 13
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#define ATH_11N_TXMAXTRY 10
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#define ATH_MGT_TXMAXTRY 4
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#define WME_BA_BMP_SIZE 64
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#define WME_MAX_BA WME_BA_BMP_SIZE
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#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
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#define TID_TO_WME_AC(_tid) \
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((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
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(((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
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(((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
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WME_AC_VO)
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#define WME_AC_BE 0
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#define WME_AC_BK 1
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#define WME_AC_VI 2
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#define WME_AC_VO 3
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#define WME_NUM_AC 4
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#define ADDBA_EXCHANGE_ATTEMPTS 10
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#define ATH_AGGR_DELIM_SZ 4
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#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
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/* number of delimiters for encryption padding */
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#define ATH_AGGR_ENCRYPTDELIM 10
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/* minimum h/w qdepth to be sustained to maximize aggregation */
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#define ATH_AGGR_MIN_QDEPTH 2
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#define ATH_AMPDU_SUBFRAME_DEFAULT 32
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#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
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#define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
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#define IEEE80211_SEQ_SEQ_SHIFT 4
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#define IEEE80211_SEQ_MAX 4096
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#define IEEE80211_MIN_AMPDU_BUF 0x8
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#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
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#define IEEE80211_WEP_IVLEN 3
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#define IEEE80211_WEP_KIDLEN 1
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#define IEEE80211_WEP_CRCLEN 4
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#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
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(IEEE80211_WEP_IVLEN + \
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IEEE80211_WEP_KIDLEN + \
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IEEE80211_WEP_CRCLEN))
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/* return whether a bit at index _n in bitmap _bm is set
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* _sz is the size of the bitmap */
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#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
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((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
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/* return block-ack bitmap index given sequence and starting sequence */
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#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
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/* returns delimiter padding required given the packet length */
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#define ATH_AGGR_GET_NDELIM(_len) \
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(((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
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(ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
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#define BAW_WITHIN(_start, _bawsz, _seqno) \
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((((_seqno) - (_start)) & 4095) < (_bawsz))
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#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
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#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
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#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
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#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
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enum ATH_AGGR_STATUS {
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ATH_AGGR_DONE,
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ATH_AGGR_BAW_CLOSED,
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ATH_AGGR_LIMITED,
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};
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struct ath_txq {
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u32 axq_qnum;
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u32 *axq_link;
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struct list_head axq_q;
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spinlock_t axq_lock;
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u32 axq_depth;
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u8 axq_aggr_depth;
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u32 axq_totalqueued;
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bool stopped;
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struct ath_buf *axq_linkbuf;
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/* first desc of the last descriptor that contains CTS */
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struct ath_desc *axq_lastdsWithCTS;
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/* final desc of the gating desc that determines whether
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lastdsWithCTS has been DMA'ed or not */
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struct ath_desc *axq_gatingds;
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struct list_head axq_acq;
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};
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#define AGGR_CLEANUP BIT(1)
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#define AGGR_ADDBA_COMPLETE BIT(2)
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#define AGGR_ADDBA_PROGRESS BIT(3)
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struct ath_atx_tid {
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struct list_head list;
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struct list_head buf_q;
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struct ath_node *an;
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struct ath_atx_ac *ac;
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struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
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u16 seq_start;
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u16 seq_next;
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u16 baw_size;
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int tidno;
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int baw_head; /* first un-acked tx buffer */
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int baw_tail; /* next unused tx buffer slot */
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int sched;
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int paused;
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u8 state;
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int addba_exchangeattempts;
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};
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struct ath_atx_ac {
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int sched;
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int qnum;
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struct list_head list;
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struct list_head tid_q;
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};
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struct ath_tx_control {
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struct ath_txq *txq;
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int if_id;
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};
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struct ath_xmit_status {
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int retries;
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int flags;
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#define ATH_TX_ERROR 0x01
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#define ATH_TX_XRETRY 0x02
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#define ATH_TX_BAR 0x04
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};
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/* All RSSI values are noise floor adjusted */
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struct ath_tx_stat {
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int rssi;
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int rssictl[ATH_MAX_ANTENNA];
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int rssiextn[ATH_MAX_ANTENNA];
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int rateieee;
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int rateKbps;
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int ratecode;
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int flags;
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u32 airtime; /* time on air per final tx rate */
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};
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struct aggr_rifs_param {
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int param_max_frames;
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int param_max_len;
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int param_rl;
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int param_al;
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struct ath_rc_series *param_rcs;
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};
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struct ath_node {
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struct ath_softc *an_sc;
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struct ath_atx_tid tid[WME_NUM_TID];
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struct ath_atx_ac ac[WME_NUM_AC];
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u16 maxampdu;
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u8 mpdudensity;
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};
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struct ath_tx {
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u16 seq_no;
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u32 txqsetup;
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int hwq_map[ATH9K_WME_AC_VO+1];
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spinlock_t txbuflock;
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struct list_head txbuf;
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struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
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struct ath_descdma txdma;
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};
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struct ath_rx {
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u8 defant;
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u8 rxotherant;
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u32 *rxlink;
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int bufsize;
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unsigned int rxfilter;
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spinlock_t rxflushlock;
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spinlock_t rxbuflock;
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struct list_head rxbuf;
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struct ath_descdma rxdma;
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};
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int ath_startrecv(struct ath_softc *sc);
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bool ath_stoprecv(struct ath_softc *sc);
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void ath_flushrecv(struct ath_softc *sc);
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u32 ath_calcrxfilter(struct ath_softc *sc);
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int ath_rx_init(struct ath_softc *sc, int nbufs);
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void ath_rx_cleanup(struct ath_softc *sc);
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int ath_rx_tasklet(struct ath_softc *sc, int flush);
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struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
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void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
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int ath_tx_setup(struct ath_softc *sc, int haltype);
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void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
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void ath_draintxq(struct ath_softc *sc,
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struct ath_txq *txq, bool retry_tx);
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void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
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void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
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void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
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int ath_tx_init(struct ath_softc *sc, int nbufs);
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int ath_tx_cleanup(struct ath_softc *sc);
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struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
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int ath_txq_update(struct ath_softc *sc, int qnum,
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struct ath9k_tx_queue_info *q);
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int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
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struct ath_tx_control *txctl);
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void ath_tx_tasklet(struct ath_softc *sc);
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void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
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bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
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int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
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u16 tid, u16 *ssn);
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int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
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void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
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/********/
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/* VIFs */
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/********/
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/*
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* Define the scheme that we select MAC address for multiple
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* BSS on the same radio. The very first VIF will just use the MAC
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* address from the EEPROM. For the next 3 VIFs, we set the
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* U/L bit (bit 1) in MAC address, and use the next two bits as the
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* index of the VIF.
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*/
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#define ATH_SET_VIF_BSSID_MASK(bssid_mask) \
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((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
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struct ath_vif {
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int av_bslot;
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enum nl80211_iftype av_opmode;
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struct ath_buf *av_bcbuf;
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struct ath_tx_control av_btxctl;
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};
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/*******************/
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/* Beacon Handling */
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/*******************/
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/*
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* Regardless of the number of beacons we stagger, (i.e. regardless of the
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* number of BSSIDs) if a given beacon does not go out even after waiting this
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* number of beacon intervals, the game's up.
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*/
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#define BSTUCK_THRESH (9 * ATH_BCBUF)
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#define ATH_BCBUF 1
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#define ATH_DEFAULT_BINTVAL 100 /* TU */
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#define ATH_DEFAULT_BMISS_LIMIT 10
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#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
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struct ath_beacon_config {
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u16 beacon_interval;
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u16 listen_interval;
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u16 dtim_period;
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u16 bmiss_timeout;
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u8 dtim_count;
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u8 tim_offset;
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union {
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u64 last_tsf;
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u8 last_tstamp[8];
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} u; /* last received beacon/probe response timestamp of this BSS. */
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};
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struct ath_beacon {
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enum {
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OK, /* no change needed */
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UPDATE, /* update pending */
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COMMIT /* beacon sent, commit change */
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} updateslot; /* slot time update fsm */
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u32 beaconq;
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u32 bmisscnt;
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u32 ast_be_xmit;
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u64 bc_tstamp;
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int bslot[ATH_BCBUF];
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int slottime;
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int slotupdate;
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struct ath9k_tx_queue_info beacon_qi;
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struct ath_descdma bdma;
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struct ath_txq *cabq;
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struct list_head bbuf;
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};
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void ath_beacon_tasklet(unsigned long data);
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void ath_beacon_config(struct ath_softc *sc, int if_id);
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int ath_beaconq_setup(struct ath_hw *ah);
|
|
int ath_beacon_alloc(struct ath_softc *sc, int if_id);
|
|
void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
|
|
|
|
/*******/
|
|
/* ANI */
|
|
/*******/
|
|
|
|
#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
|
|
#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
|
|
#define ATH_ANI_POLLINTERVAL 100 /* 100 ms */
|
|
#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
|
|
#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
|
|
|
|
struct ath_ani {
|
|
bool caldone;
|
|
int16_t noise_floor;
|
|
unsigned int longcal_timer;
|
|
unsigned int shortcal_timer;
|
|
unsigned int resetcal_timer;
|
|
unsigned int checkani_timer;
|
|
struct timer_list timer;
|
|
};
|
|
|
|
/********************/
|
|
/* LED Control */
|
|
/********************/
|
|
|
|
#define ATH_LED_PIN 1
|
|
#define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
|
|
#define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */
|
|
|
|
enum ath_led_type {
|
|
ATH_LED_RADIO,
|
|
ATH_LED_ASSOC,
|
|
ATH_LED_TX,
|
|
ATH_LED_RX
|
|
};
|
|
|
|
struct ath_led {
|
|
struct ath_softc *sc;
|
|
struct led_classdev led_cdev;
|
|
enum ath_led_type led_type;
|
|
char name[32];
|
|
bool registered;
|
|
};
|
|
|
|
/* Rfkill */
|
|
#define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
|
|
|
|
struct ath_rfkill {
|
|
struct rfkill *rfkill;
|
|
struct delayed_work rfkill_poll;
|
|
char rfkill_name[32];
|
|
};
|
|
|
|
/********************/
|
|
/* Main driver core */
|
|
/********************/
|
|
|
|
/*
|
|
* Default cache line size, in bytes.
|
|
* Used when PCI device not fully initialized by bootrom/BIOS
|
|
*/
|
|
#define DEFAULT_CACHELINE 32
|
|
#define ATH_DEFAULT_NOISE_FLOOR -95
|
|
#define ATH_REGCLASSIDS_MAX 10
|
|
#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
|
|
#define ATH_MAX_SW_RETRIES 10
|
|
#define ATH_CHAN_MAX 255
|
|
#define IEEE80211_WEP_NKID 4 /* number of key ids */
|
|
|
|
/*
|
|
* The key cache is used for h/w cipher state and also for
|
|
* tracking station state such as the current tx antenna.
|
|
* We also setup a mapping table between key cache slot indices
|
|
* and station state to short-circuit node lookups on rx.
|
|
* Different parts have different size key caches. We handle
|
|
* up to ATH_KEYMAX entries (could dynamically allocate state).
|
|
*/
|
|
#define ATH_KEYMAX 128 /* max key cache size we handle */
|
|
|
|
#define ATH_IF_ID_ANY 0xff
|
|
#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
|
|
#define ATH_RSSI_DUMMY_MARKER 0x127
|
|
#define ATH_RATE_DUMMY_MARKER 0
|
|
|
|
#define SC_OP_INVALID BIT(0)
|
|
#define SC_OP_BEACONS BIT(1)
|
|
#define SC_OP_RXAGGR BIT(2)
|
|
#define SC_OP_TXAGGR BIT(3)
|
|
#define SC_OP_CHAINMASK_UPDATE BIT(4)
|
|
#define SC_OP_FULL_RESET BIT(5)
|
|
#define SC_OP_PREAMBLE_SHORT BIT(6)
|
|
#define SC_OP_PROTECT_ENABLE BIT(7)
|
|
#define SC_OP_RXFLUSH BIT(8)
|
|
#define SC_OP_LED_ASSOCIATED BIT(9)
|
|
#define SC_OP_RFKILL_REGISTERED BIT(10)
|
|
#define SC_OP_RFKILL_SW_BLOCKED BIT(11)
|
|
#define SC_OP_RFKILL_HW_BLOCKED BIT(12)
|
|
#define SC_OP_WAIT_FOR_BEACON BIT(13)
|
|
#define SC_OP_LED_ON BIT(14)
|
|
#define SC_OP_SCANNING BIT(15)
|
|
#define SC_OP_TSF_RESET BIT(16)
|
|
|
|
struct ath_bus_ops {
|
|
void (*read_cachesize)(struct ath_softc *sc, int *csz);
|
|
void (*cleanup)(struct ath_softc *sc);
|
|
bool (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data);
|
|
};
|
|
|
|
struct ath_softc {
|
|
struct ieee80211_hw *hw;
|
|
struct device *dev;
|
|
struct tasklet_struct intr_tq;
|
|
struct tasklet_struct bcon_tasklet;
|
|
struct ath_hw *sc_ah;
|
|
void __iomem *mem;
|
|
int irq;
|
|
spinlock_t sc_resetlock;
|
|
struct mutex mutex;
|
|
|
|
u8 curbssid[ETH_ALEN];
|
|
u8 bssidmask[ETH_ALEN];
|
|
u32 intrstatus;
|
|
u32 sc_flags; /* SC_OP_* */
|
|
u16 curtxpow;
|
|
u16 curaid;
|
|
u16 cachelsz;
|
|
u8 nbcnvifs;
|
|
u16 nvifs;
|
|
u8 tx_chainmask;
|
|
u8 rx_chainmask;
|
|
u32 keymax;
|
|
DECLARE_BITMAP(keymap, ATH_KEYMAX);
|
|
u8 splitmic;
|
|
atomic_t ps_usecount;
|
|
enum ath9k_int imask;
|
|
enum ath9k_ht_extprotspacing ht_extprotspacing;
|
|
enum ath9k_ht_macmode tx_chan_width;
|
|
|
|
struct ath_config config;
|
|
struct ath_rx rx;
|
|
struct ath_tx tx;
|
|
struct ath_beacon beacon;
|
|
struct ieee80211_vif *vifs[ATH_BCBUF];
|
|
struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
|
|
struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
|
|
struct ath_rate_table *cur_rate_table;
|
|
struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
|
|
|
|
struct ath_led radio_led;
|
|
struct ath_led assoc_led;
|
|
struct ath_led tx_led;
|
|
struct ath_led rx_led;
|
|
struct delayed_work ath_led_blink_work;
|
|
int led_on_duration;
|
|
int led_off_duration;
|
|
int led_on_cnt;
|
|
int led_off_cnt;
|
|
|
|
struct ath_rfkill rf_kill;
|
|
struct ath_ani ani;
|
|
struct ath9k_node_stats nodestats;
|
|
#ifdef CONFIG_ATH9K_DEBUG
|
|
struct ath9k_debug debug;
|
|
#endif
|
|
struct ath_bus_ops *bus_ops;
|
|
};
|
|
|
|
int ath_reset(struct ath_softc *sc, bool retry_tx);
|
|
int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
|
|
int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
|
|
int ath_cabq_update(struct ath_softc *);
|
|
|
|
static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
|
|
{
|
|
sc->bus_ops->read_cachesize(sc, csz);
|
|
}
|
|
|
|
static inline void ath_bus_cleanup(struct ath_softc *sc)
|
|
{
|
|
sc->bus_ops->cleanup(sc);
|
|
}
|
|
|
|
extern struct ieee80211_ops ath9k_ops;
|
|
|
|
irqreturn_t ath_isr(int irq, void *dev);
|
|
void ath_cleanup(struct ath_softc *sc);
|
|
int ath_attach(u16 devid, struct ath_softc *sc);
|
|
void ath_detach(struct ath_softc *sc);
|
|
const char *ath_mac_bb_name(u32 mac_bb_version);
|
|
const char *ath_rf_name(u16 rf_version);
|
|
|
|
#ifdef CONFIG_PCI
|
|
int ath_pci_init(void);
|
|
void ath_pci_exit(void);
|
|
#else
|
|
static inline int ath_pci_init(void) { return 0; };
|
|
static inline void ath_pci_exit(void) {};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ATHEROS_AR71XX
|
|
int ath_ahb_init(void);
|
|
void ath_ahb_exit(void);
|
|
#else
|
|
static inline int ath_ahb_init(void) { return 0; };
|
|
static inline void ath_ahb_exit(void) {};
|
|
#endif
|
|
|
|
static inline void ath9k_ps_wakeup(struct ath_softc *sc)
|
|
{
|
|
if (atomic_inc_return(&sc->ps_usecount) == 1)
|
|
if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) {
|
|
sc->sc_ah->restore_mode = sc->sc_ah->power_mode;
|
|
ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
|
|
}
|
|
}
|
|
|
|
static inline void ath9k_ps_restore(struct ath_softc *sc)
|
|
{
|
|
if (atomic_dec_and_test(&sc->ps_usecount))
|
|
if ((sc->hw->conf.flags & IEEE80211_CONF_PS) &&
|
|
!(sc->sc_flags & SC_OP_WAIT_FOR_BEACON))
|
|
ath9k_hw_setpower(sc->sc_ah,
|
|
sc->sc_ah->restore_mode);
|
|
}
|
|
|
|
#endif /* ATH9K_H */
|