f90f54b3f3
CONFIG_HOTPLUG is going away as an option so __devexit is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
769 lines
18 KiB
C
769 lines
18 KiB
C
/*
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* Driver for the NVIDIA Tegra pinmux
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*
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* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* Derived from code:
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* Copyright (C) 2010 Google, Inc.
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* Copyright (C) 2010 NVIDIA Corporation
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* Copyright (C) 2009-2011 ST-Ericsson AB
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/slab.h>
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#include "core.h"
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#include "pinctrl-tegra.h"
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struct tegra_pmx {
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struct device *dev;
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struct pinctrl_dev *pctl;
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const struct tegra_pinctrl_soc_data *soc;
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int nbanks;
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void __iomem **regs;
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};
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static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
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{
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return readl(pmx->regs[bank] + reg);
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}
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static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
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{
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writel(val, pmx->regs[bank] + reg);
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}
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static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->soc->ngroups;
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}
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static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned group)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->soc->groups[group].name;
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}
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static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned group,
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const unsigned **pins,
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unsigned *num_pins)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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*pins = pmx->soc->groups[group].pins;
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*num_pins = pmx->soc->groups[group].npins;
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s,
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unsigned offset)
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{
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seq_printf(s, " %s", dev_name(pctldev->dev));
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}
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#endif
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static int reserve_map(struct device *dev, struct pinctrl_map **map,
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unsigned *reserved_maps, unsigned *num_maps,
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unsigned reserve)
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{
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unsigned old_num = *reserved_maps;
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unsigned new_num = *num_maps + reserve;
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struct pinctrl_map *new_map;
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if (old_num >= new_num)
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return 0;
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new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
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if (!new_map) {
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dev_err(dev, "krealloc(map) failed\n");
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return -ENOMEM;
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}
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memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
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*map = new_map;
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*reserved_maps = new_num;
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return 0;
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}
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static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
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unsigned *num_maps, const char *group,
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const char *function)
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{
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if (WARN_ON(*num_maps == *reserved_maps))
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return -ENOSPC;
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(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
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(*map)[*num_maps].data.mux.group = group;
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(*map)[*num_maps].data.mux.function = function;
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(*num_maps)++;
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return 0;
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}
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static int add_map_configs(struct device *dev, struct pinctrl_map **map,
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unsigned *reserved_maps, unsigned *num_maps,
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const char *group, unsigned long *configs,
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unsigned num_configs)
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{
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unsigned long *dup_configs;
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if (WARN_ON(*num_maps == *reserved_maps))
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return -ENOSPC;
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dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
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GFP_KERNEL);
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if (!dup_configs) {
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dev_err(dev, "kmemdup(configs) failed\n");
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return -ENOMEM;
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}
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(*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
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(*map)[*num_maps].data.configs.group_or_pin = group;
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(*map)[*num_maps].data.configs.configs = dup_configs;
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(*map)[*num_maps].data.configs.num_configs = num_configs;
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(*num_maps)++;
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return 0;
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}
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static int add_config(struct device *dev, unsigned long **configs,
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unsigned *num_configs, unsigned long config)
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{
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unsigned old_num = *num_configs;
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unsigned new_num = old_num + 1;
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unsigned long *new_configs;
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new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
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GFP_KERNEL);
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if (!new_configs) {
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dev_err(dev, "krealloc(configs) failed\n");
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return -ENOMEM;
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}
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new_configs[old_num] = config;
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*configs = new_configs;
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*num_configs = new_num;
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return 0;
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}
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void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
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struct pinctrl_map *map, unsigned num_maps)
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{
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int i;
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for (i = 0; i < num_maps; i++)
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if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
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kfree(map[i].data.configs.configs);
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kfree(map);
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}
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static const struct cfg_param {
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const char *property;
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enum tegra_pinconf_param param;
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} cfg_params[] = {
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{"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
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{"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
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{"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
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{"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
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{"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
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{"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
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{"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
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{"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
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{"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
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{"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
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{"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
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{"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
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{"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
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};
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int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
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struct device_node *np,
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struct pinctrl_map **map,
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unsigned *reserved_maps,
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unsigned *num_maps)
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{
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int ret, i;
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const char *function;
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u32 val;
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unsigned long config;
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unsigned long *configs = NULL;
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unsigned num_configs = 0;
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unsigned reserve;
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struct property *prop;
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const char *group;
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ret = of_property_read_string(np, "nvidia,function", &function);
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if (ret < 0) {
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/* EINVAL=missing, which is fine since it's optional */
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if (ret != -EINVAL)
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dev_err(dev,
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"could not parse property nvidia,function\n");
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function = NULL;
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}
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for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
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ret = of_property_read_u32(np, cfg_params[i].property, &val);
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if (!ret) {
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config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
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ret = add_config(dev, &configs, &num_configs, config);
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if (ret < 0)
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goto exit;
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/* EINVAL=missing, which is fine since it's optional */
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} else if (ret != -EINVAL) {
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dev_err(dev, "could not parse property %s\n",
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cfg_params[i].property);
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}
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}
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reserve = 0;
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if (function != NULL)
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reserve++;
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if (num_configs)
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reserve++;
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ret = of_property_count_strings(np, "nvidia,pins");
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if (ret < 0) {
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dev_err(dev, "could not parse property nvidia,pins\n");
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goto exit;
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}
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reserve *= ret;
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ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
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if (ret < 0)
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goto exit;
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of_property_for_each_string(np, "nvidia,pins", prop, group) {
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if (function) {
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ret = add_map_mux(map, reserved_maps, num_maps,
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group, function);
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if (ret < 0)
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goto exit;
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}
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if (num_configs) {
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ret = add_map_configs(dev, map, reserved_maps,
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num_maps, group, configs,
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num_configs);
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if (ret < 0)
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goto exit;
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}
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}
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ret = 0;
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exit:
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kfree(configs);
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return ret;
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}
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int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np_config,
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struct pinctrl_map **map, unsigned *num_maps)
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{
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unsigned reserved_maps;
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struct device_node *np;
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int ret;
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reserved_maps = 0;
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*map = NULL;
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*num_maps = 0;
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for_each_child_of_node(np_config, np) {
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ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
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&reserved_maps, num_maps);
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if (ret < 0) {
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tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
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return ret;
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}
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}
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return 0;
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}
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static struct pinctrl_ops tegra_pinctrl_ops = {
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.get_groups_count = tegra_pinctrl_get_groups_count,
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.get_group_name = tegra_pinctrl_get_group_name,
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.get_group_pins = tegra_pinctrl_get_group_pins,
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#ifdef CONFIG_DEBUG_FS
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.pin_dbg_show = tegra_pinctrl_pin_dbg_show,
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#endif
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.dt_node_to_map = tegra_pinctrl_dt_node_to_map,
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.dt_free_map = tegra_pinctrl_dt_free_map,
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};
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static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->soc->nfunctions;
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}
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static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
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unsigned function)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->soc->functions[function].name;
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}
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static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
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unsigned function,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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*groups = pmx->soc->functions[function].groups;
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*num_groups = pmx->soc->functions[function].ngroups;
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return 0;
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}
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static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
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unsigned group)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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const struct tegra_pingroup *g;
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int i;
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u32 val;
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g = &pmx->soc->groups[group];
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if (WARN_ON(g->mux_reg < 0))
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
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if (g->funcs[i] == function)
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break;
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}
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if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
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return -EINVAL;
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val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
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val &= ~(0x3 << g->mux_bit);
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val |= i << g->mux_bit;
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pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
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return 0;
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}
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static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
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unsigned function, unsigned group)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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const struct tegra_pingroup *g;
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u32 val;
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g = &pmx->soc->groups[group];
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|
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if (WARN_ON(g->mux_reg < 0))
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return;
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val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
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val &= ~(0x3 << g->mux_bit);
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val |= g->func_safe << g->mux_bit;
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pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
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}
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|
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static struct pinmux_ops tegra_pinmux_ops = {
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.get_functions_count = tegra_pinctrl_get_funcs_count,
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.get_function_name = tegra_pinctrl_get_func_name,
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.get_function_groups = tegra_pinctrl_get_func_groups,
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.enable = tegra_pinctrl_enable,
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.disable = tegra_pinctrl_disable,
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};
|
|
|
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static int tegra_pinconf_reg(struct tegra_pmx *pmx,
|
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const struct tegra_pingroup *g,
|
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enum tegra_pinconf_param param,
|
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bool report_err,
|
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s8 *bank, s16 *reg, s8 *bit, s8 *width)
|
|
{
|
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switch (param) {
|
|
case TEGRA_PINCONF_PARAM_PULL:
|
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*bank = g->pupd_bank;
|
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*reg = g->pupd_reg;
|
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*bit = g->pupd_bit;
|
|
*width = 2;
|
|
break;
|
|
case TEGRA_PINCONF_PARAM_TRISTATE:
|
|
*bank = g->tri_bank;
|
|
*reg = g->tri_reg;
|
|
*bit = g->tri_bit;
|
|
*width = 1;
|
|
break;
|
|
case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
|
|
*bank = g->einput_bank;
|
|
*reg = g->einput_reg;
|
|
*bit = g->einput_bit;
|
|
*width = 1;
|
|
break;
|
|
case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
|
|
*bank = g->odrain_bank;
|
|
*reg = g->odrain_reg;
|
|
*bit = g->odrain_bit;
|
|
*width = 1;
|
|
break;
|
|
case TEGRA_PINCONF_PARAM_LOCK:
|
|
*bank = g->lock_bank;
|
|
*reg = g->lock_reg;
|
|
*bit = g->lock_bit;
|
|
*width = 1;
|
|
break;
|
|
case TEGRA_PINCONF_PARAM_IORESET:
|
|
*bank = g->ioreset_bank;
|
|
*reg = g->ioreset_reg;
|
|
*bit = g->ioreset_bit;
|
|
*width = 1;
|
|
break;
|
|
case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
|
|
*bank = g->drv_bank;
|
|
*reg = g->drv_reg;
|
|
*bit = g->hsm_bit;
|
|
*width = 1;
|
|
break;
|
|
case TEGRA_PINCONF_PARAM_SCHMITT:
|
|
*bank = g->drv_bank;
|
|
*reg = g->drv_reg;
|
|
*bit = g->schmitt_bit;
|
|
*width = 1;
|
|
break;
|
|
case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
|
|
*bank = g->drv_bank;
|
|
*reg = g->drv_reg;
|
|
*bit = g->lpmd_bit;
|
|
*width = 2;
|
|
break;
|
|
case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
|
|
*bank = g->drv_bank;
|
|
*reg = g->drv_reg;
|
|
*bit = g->drvdn_bit;
|
|
*width = g->drvdn_width;
|
|
break;
|
|
case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
|
|
*bank = g->drv_bank;
|
|
*reg = g->drv_reg;
|
|
*bit = g->drvup_bit;
|
|
*width = g->drvup_width;
|
|
break;
|
|
case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
|
|
*bank = g->drv_bank;
|
|
*reg = g->drv_reg;
|
|
*bit = g->slwf_bit;
|
|
*width = g->slwf_width;
|
|
break;
|
|
case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
|
|
*bank = g->drv_bank;
|
|
*reg = g->drv_reg;
|
|
*bit = g->slwr_bit;
|
|
*width = g->slwr_width;
|
|
break;
|
|
default:
|
|
dev_err(pmx->dev, "Invalid config param %04x\n", param);
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
if (*reg < 0) {
|
|
if (report_err)
|
|
dev_err(pmx->dev,
|
|
"Config param %04x not supported on group %s\n",
|
|
param, g->name);
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
|
|
unsigned pin, unsigned long *config)
|
|
{
|
|
dev_err(pctldev->dev, "pin_config_get op not supported\n");
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
|
|
unsigned pin, unsigned long config)
|
|
{
|
|
dev_err(pctldev->dev, "pin_config_set op not supported\n");
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
|
|
unsigned group, unsigned long *config)
|
|
{
|
|
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
|
|
u16 arg;
|
|
const struct tegra_pingroup *g;
|
|
int ret;
|
|
s8 bank, bit, width;
|
|
s16 reg;
|
|
u32 val, mask;
|
|
|
|
g = &pmx->soc->groups[group];
|
|
|
|
ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
|
|
&width);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
val = pmx_readl(pmx, bank, reg);
|
|
mask = (1 << width) - 1;
|
|
arg = (val >> bit) & mask;
|
|
|
|
*config = TEGRA_PINCONF_PACK(param, arg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|
unsigned group, unsigned long config)
|
|
{
|
|
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
|
|
u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
|
|
const struct tegra_pingroup *g;
|
|
int ret;
|
|
s8 bank, bit, width;
|
|
s16 reg;
|
|
u32 val, mask;
|
|
|
|
g = &pmx->soc->groups[group];
|
|
|
|
ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
|
|
&width);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
val = pmx_readl(pmx, bank, reg);
|
|
|
|
/* LOCK can't be cleared */
|
|
if (param == TEGRA_PINCONF_PARAM_LOCK) {
|
|
if ((val & BIT(bit)) && !arg) {
|
|
dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
/* Special-case Boolean values; allow any non-zero as true */
|
|
if (width == 1)
|
|
arg = !!arg;
|
|
|
|
/* Range-check user-supplied value */
|
|
mask = (1 << width) - 1;
|
|
if (arg & ~mask) {
|
|
dev_err(pctldev->dev,
|
|
"config %lx: %x too big for %d bit register\n",
|
|
config, arg, width);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Update register */
|
|
val &= ~(mask << bit);
|
|
val |= arg << bit;
|
|
pmx_writel(pmx, val, bank, reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
|
|
struct seq_file *s, unsigned offset)
|
|
{
|
|
}
|
|
|
|
static const char *strip_prefix(const char *s)
|
|
{
|
|
const char *comma = strchr(s, ',');
|
|
if (!comma)
|
|
return s;
|
|
|
|
return comma + 1;
|
|
}
|
|
|
|
static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
|
|
struct seq_file *s, unsigned group)
|
|
{
|
|
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
const struct tegra_pingroup *g;
|
|
int i, ret;
|
|
s8 bank, bit, width;
|
|
s16 reg;
|
|
u32 val;
|
|
|
|
g = &pmx->soc->groups[group];
|
|
|
|
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
|
|
ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
|
|
&bank, ®, &bit, &width);
|
|
if (ret < 0)
|
|
continue;
|
|
|
|
val = pmx_readl(pmx, bank, reg);
|
|
val >>= bit;
|
|
val &= (1 << width) - 1;
|
|
|
|
seq_printf(s, "\n\t%s=%u",
|
|
strip_prefix(cfg_params[i].property), val);
|
|
}
|
|
}
|
|
|
|
static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
|
|
struct seq_file *s,
|
|
unsigned long config)
|
|
{
|
|
enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
|
|
u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
|
|
const char *pname = "unknown";
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
|
|
if (cfg_params[i].param == param) {
|
|
pname = cfg_params[i].property;
|
|
break;
|
|
}
|
|
}
|
|
|
|
seq_printf(s, "%s=%d", strip_prefix(pname), arg);
|
|
}
|
|
#endif
|
|
|
|
struct pinconf_ops tegra_pinconf_ops = {
|
|
.pin_config_get = tegra_pinconf_get,
|
|
.pin_config_set = tegra_pinconf_set,
|
|
.pin_config_group_get = tegra_pinconf_group_get,
|
|
.pin_config_group_set = tegra_pinconf_group_set,
|
|
#ifdef CONFIG_DEBUG_FS
|
|
.pin_config_dbg_show = tegra_pinconf_dbg_show,
|
|
.pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
|
|
.pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
|
|
#endif
|
|
};
|
|
|
|
static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
|
|
.name = "Tegra GPIOs",
|
|
.id = 0,
|
|
.base = 0,
|
|
};
|
|
|
|
static struct pinctrl_desc tegra_pinctrl_desc = {
|
|
.pctlops = &tegra_pinctrl_ops,
|
|
.pmxops = &tegra_pinmux_ops,
|
|
.confops = &tegra_pinconf_ops,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
int __devinit tegra_pinctrl_probe(struct platform_device *pdev,
|
|
const struct tegra_pinctrl_soc_data *soc_data)
|
|
{
|
|
struct tegra_pmx *pmx;
|
|
struct resource *res;
|
|
int i;
|
|
|
|
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
|
|
if (!pmx) {
|
|
dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
|
|
return -ENOMEM;
|
|
}
|
|
pmx->dev = &pdev->dev;
|
|
pmx->soc = soc_data;
|
|
|
|
tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
|
|
tegra_pinctrl_desc.name = dev_name(&pdev->dev);
|
|
tegra_pinctrl_desc.pins = pmx->soc->pins;
|
|
tegra_pinctrl_desc.npins = pmx->soc->npins;
|
|
|
|
for (i = 0; ; i++) {
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
|
if (!res)
|
|
break;
|
|
}
|
|
pmx->nbanks = i;
|
|
|
|
pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
|
|
GFP_KERNEL);
|
|
if (!pmx->regs) {
|
|
dev_err(&pdev->dev, "Can't alloc regs pointer\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
for (i = 0; i < pmx->nbanks; i++) {
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "Missing MEM resource\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!devm_request_mem_region(&pdev->dev, res->start,
|
|
resource_size(res),
|
|
dev_name(&pdev->dev))) {
|
|
dev_err(&pdev->dev,
|
|
"Couldn't request MEM resource %d\n", i);
|
|
return -ENODEV;
|
|
}
|
|
|
|
pmx->regs[i] = devm_ioremap(&pdev->dev, res->start,
|
|
resource_size(res));
|
|
if (!pmx->regs[i]) {
|
|
dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
|
|
if (!pmx->pctl) {
|
|
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
|
|
|
|
platform_set_drvdata(pdev, pmx);
|
|
|
|
dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
|
|
|
|
int tegra_pinctrl_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_pmx *pmx = platform_get_drvdata(pdev);
|
|
|
|
pinctrl_unregister(pmx->pctl);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
|