928 lines
25 KiB
C
928 lines
25 KiB
C
/**************************************************************************
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* Copyright (c) 2007-2011, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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**************************************************************************/
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#ifndef _PSB_DRV_H_
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#define _PSB_DRV_H_
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#include <linux/version.h>
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#include <linux/kref.h>
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#include <drm/drmP.h>
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#include "drm_global.h"
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#include "gem_glue.h"
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#include "psb_drm.h"
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#include "psb_reg.h"
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#include "psb_intel_drv.h"
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#include "psb_gtt.h"
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#include "psb_powermgmt.h"
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#include "mrst.h"
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/* Append new drm mode definition here, align with libdrm definition */
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#define DRM_MODE_SCALE_NO_SCALE 2
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#define DRM_MODE_CONNECTOR_MIPI 15
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enum {
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CHIP_PSB_8108 = 0, /* Poulsbo */
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CHIP_PSB_8109 = 1, /* Poulsbo */
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CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
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CHIP_MFLD_0130 = 3, /* Medfield */
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};
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#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
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#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
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/*
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* Driver definitions
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*/
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#define DRIVER_NAME "gma500"
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#define DRIVER_DESC "DRM driver for the Intel GMA500"
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#define PSB_DRM_DRIVER_DATE "2011-06-06"
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#define PSB_DRM_DRIVER_MAJOR 1
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#define PSB_DRM_DRIVER_MINOR 0
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#define PSB_DRM_DRIVER_PATCHLEVEL 0
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/*
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* Hardware offsets
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*/
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#define PSB_VDC_OFFSET 0x00000000
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#define PSB_VDC_SIZE 0x000080000
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#define MRST_MMIO_SIZE 0x0000C0000
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#define MDFLD_MMIO_SIZE 0x000100000
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#define PSB_SGX_SIZE 0x8000
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#define PSB_SGX_OFFSET 0x00040000
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#define MRST_SGX_OFFSET 0x00080000
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/*
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* PCI resource identifiers
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*/
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#define PSB_MMIO_RESOURCE 0
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#define PSB_GATT_RESOURCE 2
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#define PSB_GTT_RESOURCE 3
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/*
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* PCI configuration
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*/
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#define PSB_GMCH_CTRL 0x52
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#define PSB_BSM 0x5C
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#define _PSB_GMCH_ENABLED 0x4
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#define PSB_PGETBL_CTL 0x2020
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#define _PSB_PGETBL_ENABLED 0x00000001
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#define PSB_SGX_2D_SLAVE_PORT 0x4000
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/* To get rid of */
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#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
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#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
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/*
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* SGX side MMU definitions (these can probably go)
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*/
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/*
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* Flags for external memory type field.
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*/
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#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
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#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
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#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
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/*
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* PTE's and PDE's
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*/
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#define PSB_PDE_MASK 0x003FFFFF
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#define PSB_PDE_SHIFT 22
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#define PSB_PTE_SHIFT 12
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/*
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* Cache control
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*/
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#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
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#define PSB_PTE_WO 0x0002 /* Write only */
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#define PSB_PTE_RO 0x0004 /* Read only */
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#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
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/*
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* VDC registers and bits
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*/
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#define PSB_MSVDX_CLOCKGATING 0x2064
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#define PSB_TOPAZ_CLOCKGATING 0x2068
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#define PSB_HWSTAM 0x2098
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#define PSB_INSTPM 0x20C0
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#define PSB_INT_IDENTITY_R 0x20A4
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#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
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#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
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#define _PSB_DPST_PIPEB_FLAG (1<<4)
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#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
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#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
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#define _PSB_DPST_PIPEA_FLAG (1<<6)
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#define _PSB_PIPEA_EVENT_FLAG (1<<6)
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#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
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#define _MDFLD_MIPIA_FLAG (1<<16)
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#define _MDFLD_MIPIC_FLAG (1<<17)
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#define _PSB_IRQ_SGX_FLAG (1<<18)
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#define _PSB_IRQ_MSVDX_FLAG (1<<19)
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#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
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/* This flag includes all the display IRQ bits excepts the vblank irqs. */
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#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
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_MDFLD_PIPEB_EVENT_FLAG | \
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_PSB_PIPEA_EVENT_FLAG | \
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_PSB_VSYNC_PIPEA_FLAG | \
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_MDFLD_MIPIA_FLAG | \
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_MDFLD_MIPIC_FLAG)
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#define PSB_INT_IDENTITY_R 0x20A4
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#define PSB_INT_MASK_R 0x20A8
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#define PSB_INT_ENABLE_R 0x20A0
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#define _PSB_MMU_ER_MASK 0x0001FF00
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#define _PSB_MMU_ER_HOST (1 << 16)
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#define GPIOA 0x5010
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#define GPIOB 0x5014
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#define GPIOC 0x5018
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#define GPIOD 0x501c
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#define GPIOE 0x5020
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#define GPIOF 0x5024
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#define GPIOG 0x5028
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#define GPIOH 0x502c
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#define GPIO_CLOCK_DIR_MASK (1 << 0)
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#define GPIO_CLOCK_DIR_IN (0 << 1)
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#define GPIO_CLOCK_DIR_OUT (1 << 1)
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#define GPIO_CLOCK_VAL_MASK (1 << 2)
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#define GPIO_CLOCK_VAL_OUT (1 << 3)
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#define GPIO_CLOCK_VAL_IN (1 << 4)
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#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
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#define GPIO_DATA_DIR_MASK (1 << 8)
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#define GPIO_DATA_DIR_IN (0 << 9)
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#define GPIO_DATA_DIR_OUT (1 << 9)
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#define GPIO_DATA_VAL_MASK (1 << 10)
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#define GPIO_DATA_VAL_OUT (1 << 11)
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#define GPIO_DATA_VAL_IN (1 << 12)
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#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
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#define VCLK_DIVISOR_VGA0 0x6000
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#define VCLK_DIVISOR_VGA1 0x6004
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#define VCLK_POST_DIV 0x6010
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#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
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#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
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#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
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#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
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#define PSB_COMM_USER_IRQ (1024 >> 2)
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#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
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#define PSB_COMM_FW (2048 >> 2)
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#define PSB_UIRQ_VISTEST 1
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#define PSB_UIRQ_OOM_REPLY 2
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#define PSB_UIRQ_FIRE_TA_REPLY 3
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#define PSB_UIRQ_FIRE_RASTER_REPLY 4
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#define PSB_2D_SIZE (256*1024*1024)
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#define PSB_MAX_RELOC_PAGES 1024
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#define PSB_LOW_REG_OFFS 0x0204
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#define PSB_HIGH_REG_OFFS 0x0600
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#define PSB_NUM_VBLANKS 2
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#define PSB_2D_SIZE (256*1024*1024)
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#define PSB_MAX_RELOC_PAGES 1024
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#define PSB_LOW_REG_OFFS 0x0204
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#define PSB_HIGH_REG_OFFS 0x0600
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#define PSB_NUM_VBLANKS 2
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#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
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#define PSB_LID_DELAY (DRM_HZ / 10)
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#define MDFLD_PNW_B0 0x04
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#define MDFLD_PNW_C0 0x08
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#define MDFLD_DSR_2D_3D_0 (1 << 0)
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#define MDFLD_DSR_2D_3D_2 (1 << 1)
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#define MDFLD_DSR_CURSOR_0 (1 << 2)
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#define MDFLD_DSR_CURSOR_2 (1 << 3)
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#define MDFLD_DSR_OVERLAY_0 (1 << 4)
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#define MDFLD_DSR_OVERLAY_2 (1 << 5)
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#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
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#define MDFLD_DSR_DAMAGE_MASK_0 (1 << 0) | (1 << 2) | (1 << 4)
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#define MDFLD_DSR_DAMAGE_MASK_2 (1 << 1) | (1 << 3) | (1 << 5)
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#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
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#define MDFLD_DSR_RR 45
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#define MDFLD_DPU_ENABLE (1 << 31)
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#define MDFLD_DSR_FULLSCREEN (1 << 30)
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#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
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#define PSB_PWR_STATE_ON 1
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#define PSB_PWR_STATE_OFF 2
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#define PSB_PMPOLICY_NOPM 0
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#define PSB_PMPOLICY_CLOCKGATING 1
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#define PSB_PMPOLICY_POWERDOWN 2
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#define PSB_PMSTATE_POWERUP 0
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#define PSB_PMSTATE_CLOCKGATED 1
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#define PSB_PMSTATE_POWERDOWN 2
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#define PSB_PCIx_MSI_ADDR_LOC 0x94
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#define PSB_PCIx_MSI_DATA_LOC 0x98
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/* Medfield crystal settings */
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#define KSEL_CRYSTAL_19 1
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#define KSEL_BYPASS_19 5
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#define KSEL_BYPASS_25 6
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#define KSEL_BYPASS_83_100 7
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struct opregion_header;
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struct opregion_acpi;
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struct opregion_swsci;
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struct opregion_asle;
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struct psb_intel_opregion {
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struct opregion_header *header;
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struct opregion_acpi *acpi;
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struct opregion_swsci *swsci;
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struct opregion_asle *asle;
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int enabled;
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};
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struct psb_ops;
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struct drm_psb_private {
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struct drm_device *dev;
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const struct psb_ops *ops;
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struct psb_gtt *pg;
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/* GTT Memory manager */
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struct psb_gtt_mm *gtt_mm;
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struct page *scratch_page;
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u32 *gtt_map;
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uint32_t stolen_base;
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void *vram_addr;
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unsigned long vram_stolen_size;
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int gtt_initialized;
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u16 gmch_ctrl; /* Saved GTT setup */
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u32 pge_ctl;
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struct mutex gtt_mutex;
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struct resource *gtt_mem; /* Our PCI resource */
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struct psb_mmu_driver *mmu;
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struct psb_mmu_pd *pf_pd;
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/*
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* Register base
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*/
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uint8_t *sgx_reg;
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uint8_t *vdc_reg;
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uint32_t gatt_free_offset;
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/*
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* Fencing / irq.
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*/
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uint32_t vdc_irq_mask;
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uint32_t pipestat[PSB_NUM_PIPE];
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spinlock_t irqmask_lock;
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/*
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* Power
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*/
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bool suspended;
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bool display_power;
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int display_count;
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/*
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* Modesetting
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*/
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struct psb_intel_mode_device mode_dev;
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struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
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struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
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uint32_t num_pipe;
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/*
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* OSPM info (Power management base) (can go ?)
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*/
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uint32_t ospm_base;
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/*
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* Sizes info
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*/
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struct drm_psb_sizes_arg sizes;
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u32 fuse_reg_value;
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u32 video_device_fuse;
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/* PCI revision ID for B0:D2:F0 */
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uint8_t platform_rev_id;
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/*
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* LVDS info
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*/
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int backlight_duty_cycle; /* restore backlight to this value */
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bool panel_wants_dither;
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struct drm_display_mode *panel_fixed_mode;
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struct drm_display_mode *lfp_lvds_vbt_mode;
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struct drm_display_mode *sdvo_lvds_vbt_mode;
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struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
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struct psb_intel_i2c_chan *lvds_i2c_bus;
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/* Feature bits from the VBIOS */
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unsigned int int_tv_support:1;
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unsigned int lvds_dither:1;
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unsigned int lvds_vbt:1;
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unsigned int int_crt_support:1;
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unsigned int lvds_use_ssc:1;
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int lvds_ssc_freq;
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bool is_lvds_on;
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bool is_mipi_on;
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u32 mipi_ctrl_display;
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unsigned int core_freq;
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uint32_t iLVDS_enable;
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/* Runtime PM state */
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int rpm_enabled;
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/* MID specific */
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struct mrst_vbt vbt_data;
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struct mrst_gct_data gct_data;
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/* MIPI Panel type etc */
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int panel_id;
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bool dual_mipi; /* dual display - DPI & DBI */
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bool dpi_panel_on; /* The DPI panel power is on */
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bool dpi_panel_on2; /* The DPI panel power is on */
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bool dbi_panel_on; /* The DBI panel power is on */
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bool dbi_panel_on2; /* The DBI panel power is on */
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u32 dsr_fb_update; /* DSR FB update counter */
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/* Moorestown pipe config register value cache */
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uint32_t pipeconf;
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uint32_t pipeconf1;
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uint32_t pipeconf2;
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/* Moorestown plane control register value cache */
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uint32_t dspcntr;
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uint32_t dspcntr1;
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uint32_t dspcntr2;
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/*
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* Register state
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*/
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uint32_t saveDSPACNTR;
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uint32_t saveDSPBCNTR;
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uint32_t savePIPEACONF;
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uint32_t savePIPEBCONF;
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uint32_t savePIPEASRC;
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uint32_t savePIPEBSRC;
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uint32_t saveFPA0;
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uint32_t saveFPA1;
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uint32_t saveDPLL_A;
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uint32_t saveDPLL_A_MD;
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uint32_t saveHTOTAL_A;
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uint32_t saveHBLANK_A;
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uint32_t saveHSYNC_A;
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uint32_t saveVTOTAL_A;
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uint32_t saveVBLANK_A;
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uint32_t saveVSYNC_A;
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uint32_t saveDSPASTRIDE;
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uint32_t saveDSPASIZE;
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uint32_t saveDSPAPOS;
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uint32_t saveDSPABASE;
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uint32_t saveDSPASURF;
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uint32_t saveDSPASTATUS;
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uint32_t saveFPB0;
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uint32_t saveFPB1;
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uint32_t saveDPLL_B;
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uint32_t saveDPLL_B_MD;
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uint32_t saveHTOTAL_B;
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uint32_t saveHBLANK_B;
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uint32_t saveHSYNC_B;
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uint32_t saveVTOTAL_B;
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uint32_t saveVBLANK_B;
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uint32_t saveVSYNC_B;
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uint32_t saveDSPBSTRIDE;
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uint32_t saveDSPBSIZE;
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uint32_t saveDSPBPOS;
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uint32_t saveDSPBBASE;
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uint32_t saveDSPBSURF;
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uint32_t saveDSPBSTATUS;
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uint32_t saveVCLK_DIVISOR_VGA0;
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uint32_t saveVCLK_DIVISOR_VGA1;
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uint32_t saveVCLK_POST_DIV;
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uint32_t saveVGACNTRL;
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uint32_t saveADPA;
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uint32_t saveLVDS;
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uint32_t saveDVOA;
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uint32_t saveDVOB;
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uint32_t saveDVOC;
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uint32_t savePP_ON;
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uint32_t savePP_OFF;
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uint32_t savePP_CONTROL;
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uint32_t savePP_CYCLE;
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uint32_t savePFIT_CONTROL;
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uint32_t savePaletteA[256];
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uint32_t savePaletteB[256];
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uint32_t saveBLC_PWM_CTL2;
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uint32_t saveBLC_PWM_CTL;
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uint32_t saveCLOCKGATING;
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uint32_t saveDSPARB;
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uint32_t saveDSPATILEOFF;
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uint32_t saveDSPBTILEOFF;
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uint32_t saveDSPAADDR;
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uint32_t saveDSPBADDR;
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uint32_t savePFIT_AUTO_RATIOS;
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uint32_t savePFIT_PGM_RATIOS;
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uint32_t savePP_ON_DELAYS;
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uint32_t savePP_OFF_DELAYS;
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uint32_t savePP_DIVISOR;
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uint32_t saveBSM;
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uint32_t saveVBT;
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uint32_t saveBCLRPAT_A;
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uint32_t saveBCLRPAT_B;
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uint32_t saveDSPALINOFF;
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uint32_t saveDSPBLINOFF;
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uint32_t savePERF_MODE;
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uint32_t saveDSPFW1;
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uint32_t saveDSPFW2;
|
|
uint32_t saveDSPFW3;
|
|
uint32_t saveDSPFW4;
|
|
uint32_t saveDSPFW5;
|
|
uint32_t saveDSPFW6;
|
|
uint32_t saveCHICKENBIT;
|
|
uint32_t saveDSPACURSOR_CTRL;
|
|
uint32_t saveDSPBCURSOR_CTRL;
|
|
uint32_t saveDSPACURSOR_BASE;
|
|
uint32_t saveDSPBCURSOR_BASE;
|
|
uint32_t saveDSPACURSOR_POS;
|
|
uint32_t saveDSPBCURSOR_POS;
|
|
uint32_t save_palette_a[256];
|
|
uint32_t save_palette_b[256];
|
|
uint32_t saveOV_OVADD;
|
|
uint32_t saveOV_OGAMC0;
|
|
uint32_t saveOV_OGAMC1;
|
|
uint32_t saveOV_OGAMC2;
|
|
uint32_t saveOV_OGAMC3;
|
|
uint32_t saveOV_OGAMC4;
|
|
uint32_t saveOV_OGAMC5;
|
|
uint32_t saveOVC_OVADD;
|
|
uint32_t saveOVC_OGAMC0;
|
|
uint32_t saveOVC_OGAMC1;
|
|
uint32_t saveOVC_OGAMC2;
|
|
uint32_t saveOVC_OGAMC3;
|
|
uint32_t saveOVC_OGAMC4;
|
|
uint32_t saveOVC_OGAMC5;
|
|
|
|
/* MSI reg save */
|
|
uint32_t msi_addr;
|
|
uint32_t msi_data;
|
|
|
|
/* Medfield specific register save state */
|
|
uint32_t saveHDMIPHYMISCCTL;
|
|
uint32_t saveHDMIB_CONTROL;
|
|
uint32_t saveDSPCCNTR;
|
|
uint32_t savePIPECCONF;
|
|
uint32_t savePIPECSRC;
|
|
uint32_t saveHTOTAL_C;
|
|
uint32_t saveHBLANK_C;
|
|
uint32_t saveHSYNC_C;
|
|
uint32_t saveVTOTAL_C;
|
|
uint32_t saveVBLANK_C;
|
|
uint32_t saveVSYNC_C;
|
|
uint32_t saveDSPCSTRIDE;
|
|
uint32_t saveDSPCSIZE;
|
|
uint32_t saveDSPCPOS;
|
|
uint32_t saveDSPCSURF;
|
|
uint32_t saveDSPCSTATUS;
|
|
uint32_t saveDSPCLINOFF;
|
|
uint32_t saveDSPCTILEOFF;
|
|
uint32_t saveDSPCCURSOR_CTRL;
|
|
uint32_t saveDSPCCURSOR_BASE;
|
|
uint32_t saveDSPCCURSOR_POS;
|
|
uint32_t save_palette_c[256];
|
|
uint32_t saveOV_OVADD_C;
|
|
uint32_t saveOV_OGAMC0_C;
|
|
uint32_t saveOV_OGAMC1_C;
|
|
uint32_t saveOV_OGAMC2_C;
|
|
uint32_t saveOV_OGAMC3_C;
|
|
uint32_t saveOV_OGAMC4_C;
|
|
uint32_t saveOV_OGAMC5_C;
|
|
|
|
/* DSI register save */
|
|
uint32_t saveDEVICE_READY_REG;
|
|
uint32_t saveINTR_EN_REG;
|
|
uint32_t saveDSI_FUNC_PRG_REG;
|
|
uint32_t saveHS_TX_TIMEOUT_REG;
|
|
uint32_t saveLP_RX_TIMEOUT_REG;
|
|
uint32_t saveTURN_AROUND_TIMEOUT_REG;
|
|
uint32_t saveDEVICE_RESET_REG;
|
|
uint32_t saveDPI_RESOLUTION_REG;
|
|
uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
|
|
uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
|
|
uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
|
|
uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
|
|
uint32_t saveVERT_SYNC_PAD_COUNT_REG;
|
|
uint32_t saveVERT_BACK_PORCH_COUNT_REG;
|
|
uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
|
|
uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
|
|
uint32_t saveINIT_COUNT_REG;
|
|
uint32_t saveMAX_RET_PAK_REG;
|
|
uint32_t saveVIDEO_FMT_REG;
|
|
uint32_t saveEOT_DISABLE_REG;
|
|
uint32_t saveLP_BYTECLK_REG;
|
|
uint32_t saveHS_LS_DBI_ENABLE_REG;
|
|
uint32_t saveTXCLKESC_REG;
|
|
uint32_t saveDPHY_PARAM_REG;
|
|
uint32_t saveMIPI_CONTROL_REG;
|
|
uint32_t saveMIPI;
|
|
uint32_t saveMIPI_C;
|
|
|
|
/* DPST register save */
|
|
uint32_t saveHISTOGRAM_INT_CONTROL_REG;
|
|
uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
|
|
uint32_t savePWM_CONTROL_LOGIC;
|
|
|
|
/*
|
|
* DSI info.
|
|
*/
|
|
void * dbi_dsr_info;
|
|
void * dbi_dpu_info;
|
|
void * dsi_configs[2];
|
|
/*
|
|
* LID-Switch
|
|
*/
|
|
spinlock_t lid_lock;
|
|
struct timer_list lid_timer;
|
|
struct psb_intel_opregion opregion;
|
|
u32 *lid_state;
|
|
u32 lid_last_state;
|
|
|
|
/*
|
|
* Watchdog
|
|
*/
|
|
|
|
uint32_t apm_reg;
|
|
uint16_t apm_base;
|
|
|
|
/*
|
|
* Used for modifying backlight from
|
|
* xrandr -- consider removing and using HAL instead
|
|
*/
|
|
struct backlight_device *backlight_device;
|
|
struct drm_property *backlight_property;
|
|
uint32_t blc_adj1;
|
|
uint32_t blc_adj2;
|
|
|
|
void *fbdev;
|
|
/* DPST state */
|
|
uint32_t dsr_idle_count;
|
|
bool is_in_idle;
|
|
bool dsr_enable;
|
|
void (*exit_idle)(struct drm_device *dev, u32 update_src, void *p_surfaceAddr, bool check_hw_on_only);
|
|
|
|
/* FIXME: Arrays anyone ? */
|
|
struct mdfld_dsi_encoder *encoder0;
|
|
struct mdfld_dsi_encoder *encoder2;
|
|
struct mdfld_dsi_dbi_output * dbi_output;
|
|
struct mdfld_dsi_dbi_output * dbi_output2;
|
|
u32 bpp;
|
|
u32 bpp2;
|
|
|
|
bool dispstatus;
|
|
};
|
|
|
|
|
|
/*
|
|
* Operations for each board type
|
|
*/
|
|
|
|
struct psb_ops {
|
|
const char *name;
|
|
unsigned int accel_2d:1;
|
|
int pipes; /* Number of output pipes */
|
|
int sgx_offset; /* Base offset of SGX device */
|
|
|
|
/* Sub functions */
|
|
struct drm_crtc_helper_funcs const *crtc_helper;
|
|
struct drm_crtc_funcs const *crtc_funcs;
|
|
|
|
/* Setup hooks */
|
|
int (*chip_setup)(struct drm_device *dev);
|
|
|
|
/* Display management hooks */
|
|
int (*output_init)(struct drm_device *dev);
|
|
/* Power management hooks */
|
|
void (*init_pm)(struct drm_device *dev);
|
|
int (*save_regs)(struct drm_device *dev);
|
|
int (*restore_regs)(struct drm_device *dev);
|
|
int (*power_up)(struct drm_device *dev);
|
|
int (*power_down)(struct drm_device *dev);
|
|
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
|
/* Backlight */
|
|
int (*backlight_init)(struct drm_device *dev);
|
|
#endif
|
|
};
|
|
|
|
|
|
|
|
struct psb_mmu_driver;
|
|
|
|
extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
|
|
extern int drm_pick_crtcs(struct drm_device *dev);
|
|
|
|
static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
|
|
{
|
|
return (struct drm_psb_private *) dev->dev_private;
|
|
}
|
|
|
|
/*
|
|
* MMU stuff.
|
|
*/
|
|
|
|
extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
|
|
int trap_pagefaults,
|
|
int invalid_type,
|
|
struct drm_psb_private *dev_priv);
|
|
extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
|
|
extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
|
|
*driver);
|
|
extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
|
|
uint32_t gtt_start, uint32_t gtt_pages);
|
|
extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
|
|
int trap_pagefaults,
|
|
int invalid_type);
|
|
extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
|
|
extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
|
|
extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
|
|
unsigned long address,
|
|
uint32_t num_pages);
|
|
extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
|
|
uint32_t start_pfn,
|
|
unsigned long address,
|
|
uint32_t num_pages, int type);
|
|
extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
|
|
unsigned long *pfn);
|
|
|
|
/*
|
|
* Enable / disable MMU for different requestors.
|
|
*/
|
|
|
|
|
|
extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
|
|
extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
|
|
unsigned long address, uint32_t num_pages,
|
|
uint32_t desired_tile_stride,
|
|
uint32_t hw_tile_stride, int type);
|
|
extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
|
|
unsigned long address, uint32_t num_pages,
|
|
uint32_t desired_tile_stride,
|
|
uint32_t hw_tile_stride);
|
|
/*
|
|
*psb_irq.c
|
|
*/
|
|
|
|
extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
|
|
extern int psb_irq_enable_dpst(struct drm_device *dev);
|
|
extern int psb_irq_disable_dpst(struct drm_device *dev);
|
|
extern void psb_irq_preinstall(struct drm_device *dev);
|
|
extern int psb_irq_postinstall(struct drm_device *dev);
|
|
extern void psb_irq_uninstall(struct drm_device *dev);
|
|
extern void psb_irq_turn_on_dpst(struct drm_device *dev);
|
|
extern void psb_irq_turn_off_dpst(struct drm_device *dev);
|
|
|
|
extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
|
|
extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
|
|
extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
|
|
extern int psb_enable_vblank(struct drm_device *dev, int crtc);
|
|
extern void psb_disable_vblank(struct drm_device *dev, int crtc);
|
|
void
|
|
psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
|
|
|
|
void
|
|
psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
|
|
|
|
extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
|
|
|
|
extern int mdfld_enable_te(struct drm_device *dev, int pipe);
|
|
extern void mdfld_disable_te(struct drm_device *dev, int pipe);
|
|
|
|
/*
|
|
* psb_opregion.c
|
|
*/
|
|
extern int psb_intel_opregion_init(struct drm_device *dev);
|
|
|
|
/*
|
|
*psb_fb.c
|
|
*/
|
|
extern int psbfb_probed(struct drm_device *dev);
|
|
extern int psbfb_remove(struct drm_device *dev,
|
|
struct drm_framebuffer *fb);
|
|
/*
|
|
* psb_2d.c
|
|
*/
|
|
extern void psbfb_copyarea(struct fb_info *info,
|
|
const struct fb_copyarea *region);
|
|
extern int psbfb_sync(struct fb_info *info);
|
|
extern void psb_spank(struct drm_psb_private *dev_priv);
|
|
extern int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
|
|
unsigned size);
|
|
|
|
/*
|
|
* psb_reset.c
|
|
*/
|
|
|
|
extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
|
|
extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
|
|
extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
|
|
|
|
/* modesetting */
|
|
extern void psb_modeset_init(struct drm_device *dev);
|
|
extern void psb_modeset_cleanup(struct drm_device *dev);
|
|
extern int psb_fbdev_init(struct drm_device *dev);
|
|
|
|
/* backlight.c */
|
|
int gma_backlight_init(struct drm_device *dev);
|
|
void gma_backlight_exit(struct drm_device *dev);
|
|
|
|
/* mrst_crtc.c */
|
|
extern const struct drm_crtc_helper_funcs mrst_helper_funcs;
|
|
|
|
/* mrst_lvds.c */
|
|
extern void mrst_lvds_init(struct drm_device *dev,
|
|
struct psb_intel_mode_device *mode_dev);
|
|
|
|
/* psb_intel_display.c */
|
|
extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
|
|
extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
|
|
|
|
/* psb_intel_lvds.c */
|
|
extern void psb_intel_lvds_prepare(struct drm_encoder *encoder);
|
|
extern void psb_intel_lvds_commit(struct drm_encoder *encoder);
|
|
extern const struct drm_connector_helper_funcs
|
|
psb_intel_lvds_connector_helper_funcs;
|
|
extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
|
|
|
|
/* psb_gem.c */
|
|
extern int psb_gem_init_object(struct drm_gem_object *obj);
|
|
extern void psb_gem_free_object(struct drm_gem_object *obj);
|
|
extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
|
|
struct drm_file *file);
|
|
extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
|
|
struct drm_mode_create_dumb *args);
|
|
extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
|
|
uint32_t handle);
|
|
extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
|
|
uint32_t handle, uint64_t *offset);
|
|
extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
|
|
|
|
/* psb_device.c */
|
|
extern const struct psb_ops psb_chip_ops;
|
|
|
|
/* mrst_device.c */
|
|
extern const struct psb_ops mrst_chip_ops;
|
|
|
|
/* mdfld_device.c */
|
|
extern const struct psb_ops mdfld_chip_ops;
|
|
|
|
/*
|
|
* Debug print bits setting
|
|
*/
|
|
#define PSB_D_GENERAL (1 << 0)
|
|
#define PSB_D_INIT (1 << 1)
|
|
#define PSB_D_IRQ (1 << 2)
|
|
#define PSB_D_ENTRY (1 << 3)
|
|
/* debug the get H/V BP/FP count */
|
|
#define PSB_D_HV (1 << 4)
|
|
#define PSB_D_DBI_BF (1 << 5)
|
|
#define PSB_D_PM (1 << 6)
|
|
#define PSB_D_RENDER (1 << 7)
|
|
#define PSB_D_REG (1 << 8)
|
|
#define PSB_D_MSVDX (1 << 9)
|
|
#define PSB_D_TOPAZ (1 << 10)
|
|
|
|
extern int drm_psb_no_fb;
|
|
extern int drm_idle_check_interval;
|
|
|
|
/*
|
|
* Utilities
|
|
*/
|
|
|
|
static inline u32 MRST_MSG_READ32(uint port, uint offset)
|
|
{
|
|
int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
|
|
uint32_t ret_val = 0;
|
|
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
|
pci_write_config_dword(pci_root, 0xD0, mcr);
|
|
pci_read_config_dword(pci_root, 0xD4, &ret_val);
|
|
pci_dev_put(pci_root);
|
|
return ret_val;
|
|
}
|
|
static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
|
|
{
|
|
int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
|
|
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
|
pci_write_config_dword(pci_root, 0xD4, value);
|
|
pci_write_config_dword(pci_root, 0xD0, mcr);
|
|
pci_dev_put(pci_root);
|
|
}
|
|
static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
|
|
{
|
|
int mcr = (0x10<<24) | (port << 16) | (offset << 8);
|
|
uint32_t ret_val = 0;
|
|
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
|
pci_write_config_dword(pci_root, 0xD0, mcr);
|
|
pci_read_config_dword(pci_root, 0xD4, &ret_val);
|
|
pci_dev_put(pci_root);
|
|
return ret_val;
|
|
}
|
|
static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
|
|
{
|
|
int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
|
|
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
|
pci_write_config_dword(pci_root, 0xD4, value);
|
|
pci_write_config_dword(pci_root, 0xD0, mcr);
|
|
pci_dev_put(pci_root);
|
|
}
|
|
|
|
static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
return ioread32(dev_priv->vdc_reg + reg);
|
|
}
|
|
|
|
#define REG_READ(reg) REGISTER_READ(dev, (reg))
|
|
|
|
static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
|
|
uint32_t val)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
iowrite32((val), dev_priv->vdc_reg + (reg));
|
|
}
|
|
|
|
#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
|
|
|
|
static inline void REGISTER_WRITE16(struct drm_device *dev,
|
|
uint32_t reg, uint32_t val)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
iowrite16((val), dev_priv->vdc_reg + (reg));
|
|
}
|
|
|
|
#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
|
|
|
|
static inline void REGISTER_WRITE8(struct drm_device *dev,
|
|
uint32_t reg, uint32_t val)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
iowrite8((val), dev_priv->vdc_reg + (reg));
|
|
}
|
|
|
|
#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
|
|
|
|
#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
|
|
#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
|
|
|
|
/* #define TRAP_SGX_PM_FAULT 1 */
|
|
#ifdef TRAP_SGX_PM_FAULT
|
|
#define PSB_RSGX32(_offs) \
|
|
({ \
|
|
if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
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printk(KERN_ERR \
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|
"access sgx when it's off!! (READ) %s, %d\n", \
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|
__FILE__, __LINE__); \
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|
melay(1000); \
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|
} \
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ioread32(dev_priv->sgx_reg + (_offs)); \
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|
})
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#else
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#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
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#endif
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#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
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|
|
|
#define MSVDX_REG_DUMP 0
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|
|
|
#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
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|
#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
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|
|
|
#endif
|