7085689ed1
Our prior mode of operation didn't allow nested interrupts because it makes the interrupt code much simpler. However, nested interrupts are better for latency. This code uses the EIEM register to simulate level interrupts and thus achieve nesting. Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
57 lines
1.3 KiB
C
57 lines
1.3 KiB
C
/*
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* include/asm-parisc/irq.h
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*
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* Copyright 2005 Matthew Wilcox <matthew@wil.cx>
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*/
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#ifndef _ASM_PARISC_IRQ_H
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#define _ASM_PARISC_IRQ_H
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#include <linux/cpumask.h>
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#include <asm/types.h>
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#define NO_IRQ (-1)
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#ifdef CONFIG_GSC
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#define GSC_IRQ_BASE 16
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#define GSC_IRQ_MAX 63
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#define CPU_IRQ_BASE 64
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#else
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#define CPU_IRQ_BASE 16
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#endif
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#define TIMER_IRQ (CPU_IRQ_BASE + 0)
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#define IPI_IRQ (CPU_IRQ_BASE + 1)
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#define CPU_IRQ_MAX (CPU_IRQ_BASE + (BITS_PER_LONG - 1))
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#define NR_IRQS (CPU_IRQ_MAX + 1)
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static __inline__ int irq_canonicalize(int irq)
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{
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return (irq == 2) ? 9 : irq;
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}
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struct irq_chip;
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/*
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* Some useful "we don't have to do anything here" handlers. Should
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* probably be provided by the generic code.
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*/
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void no_ack_irq(unsigned int irq);
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void no_end_irq(unsigned int irq);
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void cpu_ack_irq(unsigned int irq);
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void cpu_end_irq(unsigned int irq);
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extern int txn_alloc_irq(unsigned int nbits);
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extern int txn_claim_irq(int);
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extern unsigned int txn_alloc_data(unsigned int);
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extern unsigned long txn_alloc_addr(unsigned int);
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extern unsigned long txn_affinity_addr(unsigned int irq, int cpu);
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extern int cpu_claim_irq(unsigned int irq, struct irq_chip *, void *);
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extern int cpu_check_affinity(unsigned int irq, cpumask_t *dest);
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/* soft power switch support (power.c) */
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extern struct tasklet_struct power_tasklet;
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#endif /* _ASM_PARISC_IRQ_H */
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