1116 lines
28 KiB
C
1116 lines
28 KiB
C
/*
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* AD7190 AD7192 AD7195 SPI ADC driver
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*
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* Copyright 2011-2012 Analog Devices Inc.
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*
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* Licensed under the GPL-2.
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*/
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/sysfs.h>
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#include <linux/spi/spi.h>
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#include <linux/regulator/consumer.h>
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#include <linux/err.h>
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#include <linux/sched.h>
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#include <linux/delay.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#include "ad7192.h"
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/* Registers */
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#define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
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#define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
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#define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
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#define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
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#define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
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#define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
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#define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
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#define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit
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* (AD7792)/24-bit (AD7192)) */
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#define AD7192_REG_FULLSALE 7 /* Full-Scale Register
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* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
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/* Communications Register Bit Designations (AD7192_REG_COMM) */
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#define AD7192_COMM_WEN (1 << 7) /* Write Enable */
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#define AD7192_COMM_WRITE (0 << 6) /* Write Operation */
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#define AD7192_COMM_READ (1 << 6) /* Read Operation */
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#define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
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#define AD7192_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
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/* Status Register Bit Designations (AD7192_REG_STAT) */
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#define AD7192_STAT_RDY (1 << 7) /* Ready */
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#define AD7192_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
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#define AD7192_STAT_NOREF (1 << 5) /* Error no external reference */
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#define AD7192_STAT_PARITY (1 << 4) /* Parity */
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#define AD7192_STAT_CH3 (1 << 2) /* Channel 3 */
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#define AD7192_STAT_CH2 (1 << 1) /* Channel 2 */
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#define AD7192_STAT_CH1 (1 << 0) /* Channel 1 */
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/* Mode Register Bit Designations (AD7192_REG_MODE) */
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#define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
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#define AD7192_MODE_DAT_STA (1 << 20) /* Status Register transmission */
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#define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
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#define AD7192_MODE_SINC3 (1 << 15) /* SINC3 Filter Select */
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#define AD7192_MODE_ACX (1 << 14) /* AC excitation enable(AD7195 only)*/
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#define AD7192_MODE_ENPAR (1 << 13) /* Parity Enable */
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#define AD7192_MODE_CLKDIV (1 << 12) /* Clock divide by 2 (AD7190/2 only)*/
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#define AD7192_MODE_SCYCLE (1 << 11) /* Single cycle conversion */
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#define AD7192_MODE_REJ60 (1 << 10) /* 50/60Hz notch filter */
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#define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
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/* Mode Register: AD7192_MODE_SEL options */
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#define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
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#define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
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#define AD7192_MODE_IDLE 2 /* Idle Mode */
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#define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
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#define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
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#define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
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#define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
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#define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
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/* Mode Register: AD7192_MODE_CLKSRC options */
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#define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected
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* from MCLK1 to MCLK2 */
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#define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
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#define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not
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* available at the MCLK2 pin */
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#define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available
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* at the MCLK2 pin */
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/* Configuration Register Bit Designations (AD7192_REG_CONF) */
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#define AD7192_CONF_CHOP (1 << 23) /* CHOP enable */
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#define AD7192_CONF_REFSEL (1 << 20) /* REFIN1/REFIN2 Reference Select */
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#define AD7192_CONF_CHAN(x) (((x) & 0xFF) << 8) /* Channel select */
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#define AD7192_CONF_BURN (1 << 7) /* Burnout current enable */
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#define AD7192_CONF_REFDET (1 << 6) /* Reference detect enable */
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#define AD7192_CONF_BUF (1 << 4) /* Buffered Mode Enable */
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#define AD7192_CONF_UNIPOLAR (1 << 3) /* Unipolar/Bipolar Enable */
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#define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
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#define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */
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#define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */
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#define AD7192_CH_TEMP 2 /* Temp Sensor */
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#define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */
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#define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */
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#define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */
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#define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */
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#define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */
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/* ID Register Bit Designations (AD7192_REG_ID) */
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#define ID_AD7190 0x4
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#define ID_AD7192 0x0
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#define ID_AD7195 0x6
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#define AD7192_ID_MASK 0x0F
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/* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
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#define AD7192_GPOCON_BPDSW (1 << 6) /* Bridge power-down switch enable */
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#define AD7192_GPOCON_GP32EN (1 << 5) /* Digital Output P3 and P2 enable */
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#define AD7192_GPOCON_GP10EN (1 << 4) /* Digital Output P1 and P0 enable */
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#define AD7192_GPOCON_P3DAT (1 << 3) /* P3 state */
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#define AD7192_GPOCON_P2DAT (1 << 2) /* P2 state */
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#define AD7192_GPOCON_P1DAT (1 << 1) /* P1 state */
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#define AD7192_GPOCON_P0DAT (1 << 0) /* P0 state */
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#define AD7192_INT_FREQ_MHz 4915200
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/* NOTE:
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* The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
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* In order to avoid contentions on the SPI bus, it's therefore necessary
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* to use spi bus locking.
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*
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* The DOUT/RDY output must also be wired to an interrupt capable GPIO.
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*/
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struct ad7192_state {
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struct spi_device *spi;
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struct iio_trigger *trig;
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struct regulator *reg;
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struct ad7192_platform_data *pdata;
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wait_queue_head_t wq_data_avail;
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bool done;
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bool irq_dis;
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u16 int_vref_mv;
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u32 mclk;
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u32 f_order;
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u32 mode;
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u32 conf;
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u32 scale_avail[8][2];
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long available_scan_masks[9];
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u8 gpocon;
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u8 devid;
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/*
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* DMA (thus cache coherency maintenance) requires the
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* transfer buffers to live in their own cache lines.
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*/
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u8 data[4] ____cacheline_aligned;
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};
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static int __ad7192_write_reg(struct ad7192_state *st, bool locked,
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bool cs_change, unsigned char reg,
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unsigned size, unsigned val)
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{
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u8 *data = st->data;
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struct spi_transfer t = {
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.tx_buf = data,
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.len = size + 1,
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.cs_change = cs_change,
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};
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struct spi_message m;
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data[0] = AD7192_COMM_WRITE | AD7192_COMM_ADDR(reg);
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switch (size) {
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case 3:
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data[1] = val >> 16;
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data[2] = val >> 8;
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data[3] = val;
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break;
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case 2:
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data[1] = val >> 8;
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data[2] = val;
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break;
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case 1:
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data[1] = val;
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break;
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default:
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return -EINVAL;
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}
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spi_message_init(&m);
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spi_message_add_tail(&t, &m);
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if (locked)
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return spi_sync_locked(st->spi, &m);
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else
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return spi_sync(st->spi, &m);
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}
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static int ad7192_write_reg(struct ad7192_state *st,
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unsigned reg, unsigned size, unsigned val)
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{
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return __ad7192_write_reg(st, false, false, reg, size, val);
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}
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static int __ad7192_read_reg(struct ad7192_state *st, bool locked,
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bool cs_change, unsigned char reg,
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int *val, unsigned size)
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{
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u8 *data = st->data;
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int ret;
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struct spi_transfer t[] = {
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{
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.tx_buf = data,
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.len = 1,
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}, {
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.rx_buf = data,
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.len = size,
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.cs_change = cs_change,
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},
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};
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struct spi_message m;
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data[0] = AD7192_COMM_READ | AD7192_COMM_ADDR(reg);
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spi_message_init(&m);
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spi_message_add_tail(&t[0], &m);
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spi_message_add_tail(&t[1], &m);
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if (locked)
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ret = spi_sync_locked(st->spi, &m);
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else
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ret = spi_sync(st->spi, &m);
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if (ret < 0)
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return ret;
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switch (size) {
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case 3:
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*val = data[0] << 16 | data[1] << 8 | data[2];
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break;
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case 2:
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*val = data[0] << 8 | data[1];
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break;
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case 1:
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*val = data[0];
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int ad7192_read_reg(struct ad7192_state *st,
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unsigned reg, int *val, unsigned size)
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{
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return __ad7192_read_reg(st, 0, 0, reg, val, size);
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}
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static int ad7192_read(struct ad7192_state *st, unsigned ch,
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unsigned len, int *val)
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{
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int ret;
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st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
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AD7192_CONF_CHAN(1 << ch);
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st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
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AD7192_MODE_SEL(AD7192_MODE_SINGLE);
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ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
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spi_bus_lock(st->spi->master);
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st->done = false;
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ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode);
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if (ret < 0)
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goto out;
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st->irq_dis = false;
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enable_irq(st->spi->irq);
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wait_event_interruptible(st->wq_data_avail, st->done);
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ret = __ad7192_read_reg(st, 1, 0, AD7192_REG_DATA, val, len);
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out:
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spi_bus_unlock(st->spi->master);
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return ret;
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}
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static int ad7192_calibrate(struct ad7192_state *st, unsigned mode, unsigned ch)
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{
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int ret;
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st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
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AD7192_CONF_CHAN(1 << ch);
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st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | AD7192_MODE_SEL(mode);
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ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
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spi_bus_lock(st->spi->master);
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st->done = false;
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ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3,
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(st->devid != ID_AD7195) ?
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st->mode | AD7192_MODE_CLKDIV :
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st->mode);
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if (ret < 0)
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goto out;
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st->irq_dis = false;
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enable_irq(st->spi->irq);
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wait_event_interruptible(st->wq_data_avail, st->done);
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st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
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AD7192_MODE_SEL(AD7192_MODE_IDLE);
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ret = __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode);
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out:
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spi_bus_unlock(st->spi->master);
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return ret;
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}
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static const u8 ad7192_calib_arr[8][2] = {
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{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
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{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
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{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
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{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
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{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
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{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
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{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
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{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
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};
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static int ad7192_calibrate_all(struct ad7192_state *st)
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{
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int i, ret;
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for (i = 0; i < ARRAY_SIZE(ad7192_calib_arr); i++) {
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ret = ad7192_calibrate(st, ad7192_calib_arr[i][0],
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ad7192_calib_arr[i][1]);
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if (ret)
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goto out;
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}
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return 0;
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out:
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dev_err(&st->spi->dev, "Calibration failed\n");
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return ret;
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}
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static int ad7192_setup(struct ad7192_state *st)
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{
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struct iio_dev *indio_dev = spi_get_drvdata(st->spi);
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struct ad7192_platform_data *pdata = st->pdata;
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unsigned long long scale_uv;
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int i, ret, id;
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u8 ones[6];
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/* reset the serial interface */
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memset(&ones, 0xFF, 6);
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ret = spi_write(st->spi, &ones, 6);
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if (ret < 0)
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goto out;
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msleep(1); /* Wait for at least 500us */
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/* write/read test for device presence */
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ret = ad7192_read_reg(st, AD7192_REG_ID, &id, 1);
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if (ret)
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goto out;
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id &= AD7192_ID_MASK;
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if (id != st->devid)
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dev_warn(&st->spi->dev, "device ID query failed (0x%X)\n", id);
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switch (pdata->clock_source_sel) {
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case AD7192_CLK_EXT_MCLK1_2:
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case AD7192_CLK_EXT_MCLK2:
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st->mclk = AD7192_INT_FREQ_MHz;
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break;
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case AD7192_CLK_INT:
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case AD7192_CLK_INT_CO:
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if (pdata->ext_clk_Hz)
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st->mclk = pdata->ext_clk_Hz;
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else
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st->mclk = AD7192_INT_FREQ_MHz;
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break;
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default:
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ret = -EINVAL;
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goto out;
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}
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st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
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AD7192_MODE_CLKSRC(pdata->clock_source_sel) |
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AD7192_MODE_RATE(480);
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st->conf = AD7192_CONF_GAIN(0);
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if (pdata->rej60_en)
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st->mode |= AD7192_MODE_REJ60;
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if (pdata->sinc3_en)
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st->mode |= AD7192_MODE_SINC3;
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if (pdata->refin2_en && (st->devid != ID_AD7195))
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st->conf |= AD7192_CONF_REFSEL;
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if (pdata->chop_en) {
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st->conf |= AD7192_CONF_CHOP;
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if (pdata->sinc3_en)
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st->f_order = 3; /* SINC 3rd order */
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else
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st->f_order = 4; /* SINC 4th order */
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} else {
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st->f_order = 1;
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}
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if (pdata->buf_en)
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st->conf |= AD7192_CONF_BUF;
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if (pdata->unipolar_en)
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st->conf |= AD7192_CONF_UNIPOLAR;
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if (pdata->burnout_curr_en)
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st->conf |= AD7192_CONF_BURN;
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ret = ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
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if (ret)
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goto out;
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ret = ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
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if (ret)
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goto out;
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ret = ad7192_calibrate_all(st);
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if (ret)
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goto out;
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/* Populate available ADC input ranges */
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for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
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scale_uv = ((u64)st->int_vref_mv * 100000000)
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>> (indio_dev->channels[0].scan_type.realbits -
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((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
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scale_uv >>= i;
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st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
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st->scale_avail[i][0] = scale_uv;
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}
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return 0;
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out:
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dev_err(&st->spi->dev, "setup failed\n");
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return ret;
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}
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static int ad7192_ring_preenable(struct iio_dev *indio_dev)
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{
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
unsigned channel;
|
|
int ret;
|
|
|
|
if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
|
|
return -EINVAL;
|
|
|
|
ret = iio_sw_buffer_preenable(indio_dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
channel = find_first_bit(indio_dev->active_scan_mask,
|
|
indio_dev->masklength);
|
|
|
|
st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
|
|
AD7192_MODE_SEL(AD7192_MODE_CONT);
|
|
st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
|
|
AD7192_CONF_CHAN(1 << indio_dev->channels[channel].address);
|
|
|
|
ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
|
|
|
|
spi_bus_lock(st->spi->master);
|
|
__ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode);
|
|
|
|
st->irq_dis = false;
|
|
enable_irq(st->spi->irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ad7192_ring_postdisable(struct iio_dev *indio_dev)
|
|
{
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
|
|
st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
|
|
AD7192_MODE_SEL(AD7192_MODE_IDLE);
|
|
|
|
st->done = false;
|
|
wait_event_interruptible(st->wq_data_avail, st->done);
|
|
|
|
if (!st->irq_dis)
|
|
disable_irq_nosync(st->spi->irq);
|
|
|
|
__ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode);
|
|
|
|
return spi_bus_unlock(st->spi->master);
|
|
}
|
|
|
|
/**
|
|
* ad7192_trigger_handler() bh of trigger launched polling to ring buffer
|
|
**/
|
|
static irqreturn_t ad7192_trigger_handler(int irq, void *p)
|
|
{
|
|
struct iio_poll_func *pf = p;
|
|
struct iio_dev *indio_dev = pf->indio_dev;
|
|
struct iio_buffer *ring = indio_dev->buffer;
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
s64 dat64[2];
|
|
s32 *dat32 = (s32 *)dat64;
|
|
|
|
if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
|
|
__ad7192_read_reg(st, 1, 1, AD7192_REG_DATA,
|
|
dat32,
|
|
indio_dev->channels[0].scan_type.realbits/8);
|
|
|
|
/* Guaranteed to be aligned with 8 byte boundary */
|
|
if (indio_dev->scan_timestamp)
|
|
dat64[1] = pf->timestamp;
|
|
|
|
ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
|
|
|
|
iio_trigger_notify_done(indio_dev->trig);
|
|
st->irq_dis = false;
|
|
enable_irq(st->spi->irq);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static const struct iio_buffer_setup_ops ad7192_ring_setup_ops = {
|
|
.preenable = &ad7192_ring_preenable,
|
|
.postenable = &iio_triggered_buffer_postenable,
|
|
.predisable = &iio_triggered_buffer_predisable,
|
|
.postdisable = &ad7192_ring_postdisable,
|
|
};
|
|
|
|
static int ad7192_register_ring_funcs_and_init(struct iio_dev *indio_dev)
|
|
{
|
|
return iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
|
|
&ad7192_trigger_handler, &ad7192_ring_setup_ops);
|
|
}
|
|
|
|
static void ad7192_ring_cleanup(struct iio_dev *indio_dev)
|
|
{
|
|
iio_triggered_buffer_cleanup(indio_dev);
|
|
}
|
|
|
|
/**
|
|
* ad7192_data_rdy_trig_poll() the event handler for the data rdy trig
|
|
**/
|
|
static irqreturn_t ad7192_data_rdy_trig_poll(int irq, void *private)
|
|
{
|
|
struct ad7192_state *st = iio_priv(private);
|
|
|
|
st->done = true;
|
|
wake_up_interruptible(&st->wq_data_avail);
|
|
disable_irq_nosync(irq);
|
|
st->irq_dis = true;
|
|
iio_trigger_poll(st->trig, iio_get_time_ns());
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static struct iio_trigger_ops ad7192_trigger_ops = {
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static int ad7192_probe_trigger(struct iio_dev *indio_dev)
|
|
{
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
int ret;
|
|
|
|
st->trig = iio_trigger_alloc("%s-dev%d",
|
|
spi_get_device_id(st->spi)->name,
|
|
indio_dev->id);
|
|
if (st->trig == NULL) {
|
|
ret = -ENOMEM;
|
|
goto error_ret;
|
|
}
|
|
st->trig->ops = &ad7192_trigger_ops;
|
|
ret = request_irq(st->spi->irq,
|
|
ad7192_data_rdy_trig_poll,
|
|
IRQF_TRIGGER_LOW,
|
|
spi_get_device_id(st->spi)->name,
|
|
indio_dev);
|
|
if (ret)
|
|
goto error_free_trig;
|
|
|
|
disable_irq_nosync(st->spi->irq);
|
|
st->irq_dis = true;
|
|
st->trig->dev.parent = &st->spi->dev;
|
|
st->trig->private_data = indio_dev;
|
|
|
|
ret = iio_trigger_register(st->trig);
|
|
|
|
/* select default trigger */
|
|
indio_dev->trig = st->trig;
|
|
if (ret)
|
|
goto error_free_irq;
|
|
|
|
return 0;
|
|
|
|
error_free_irq:
|
|
free_irq(st->spi->irq, indio_dev);
|
|
error_free_trig:
|
|
iio_trigger_free(st->trig);
|
|
error_ret:
|
|
return ret;
|
|
}
|
|
|
|
static void ad7192_remove_trigger(struct iio_dev *indio_dev)
|
|
{
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
|
|
iio_trigger_unregister(st->trig);
|
|
free_irq(st->spi->irq, indio_dev);
|
|
iio_trigger_free(st->trig);
|
|
}
|
|
|
|
static ssize_t ad7192_read_frequency(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
|
|
return sprintf(buf, "%d\n", st->mclk /
|
|
(st->f_order * 1024 * AD7192_MODE_RATE(st->mode)));
|
|
}
|
|
|
|
static ssize_t ad7192_write_frequency(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf,
|
|
size_t len)
|
|
{
|
|
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
unsigned long lval;
|
|
int div, ret;
|
|
|
|
ret = strict_strtoul(buf, 10, &lval);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mutex_lock(&indio_dev->mlock);
|
|
if (iio_buffer_enabled(indio_dev)) {
|
|
mutex_unlock(&indio_dev->mlock);
|
|
return -EBUSY;
|
|
}
|
|
|
|
div = st->mclk / (lval * st->f_order * 1024);
|
|
if (div < 1 || div > 1023) {
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
st->mode &= ~AD7192_MODE_RATE(-1);
|
|
st->mode |= AD7192_MODE_RATE(div);
|
|
ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
|
|
|
|
out:
|
|
mutex_unlock(&indio_dev->mlock);
|
|
|
|
return ret ? ret : len;
|
|
}
|
|
|
|
static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
|
|
ad7192_read_frequency,
|
|
ad7192_write_frequency);
|
|
|
|
|
|
static ssize_t ad7192_show_scale_available(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
int i, len = 0;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
|
|
len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
|
|
st->scale_avail[i][1]);
|
|
|
|
len += sprintf(buf + len, "\n");
|
|
|
|
return len;
|
|
}
|
|
|
|
static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available,
|
|
in_voltage-voltage_scale_available,
|
|
S_IRUGO, ad7192_show_scale_available, NULL, 0);
|
|
|
|
static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
|
|
ad7192_show_scale_available, NULL, 0);
|
|
|
|
static ssize_t ad7192_show_ac_excitation(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
|
|
return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
|
|
}
|
|
|
|
static ssize_t ad7192_show_bridge_switch(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
|
|
return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
|
|
}
|
|
|
|
static ssize_t ad7192_set(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf,
|
|
size_t len)
|
|
{
|
|
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
|
|
int ret;
|
|
bool val;
|
|
|
|
ret = strtobool(buf, &val);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
mutex_lock(&indio_dev->mlock);
|
|
if (iio_buffer_enabled(indio_dev)) {
|
|
mutex_unlock(&indio_dev->mlock);
|
|
return -EBUSY;
|
|
}
|
|
|
|
switch ((u32) this_attr->address) {
|
|
case AD7192_REG_GPOCON:
|
|
if (val)
|
|
st->gpocon |= AD7192_GPOCON_BPDSW;
|
|
else
|
|
st->gpocon &= ~AD7192_GPOCON_BPDSW;
|
|
|
|
ad7192_write_reg(st, AD7192_REG_GPOCON, 1, st->gpocon);
|
|
break;
|
|
case AD7192_REG_MODE:
|
|
if (val)
|
|
st->mode |= AD7192_MODE_ACX;
|
|
else
|
|
st->mode &= ~AD7192_MODE_ACX;
|
|
|
|
ad7192_write_reg(st, AD7192_REG_GPOCON, 3, st->mode);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
mutex_unlock(&indio_dev->mlock);
|
|
|
|
return ret ? ret : len;
|
|
}
|
|
|
|
static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR,
|
|
ad7192_show_bridge_switch, ad7192_set,
|
|
AD7192_REG_GPOCON);
|
|
|
|
static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR,
|
|
ad7192_show_ac_excitation, ad7192_set,
|
|
AD7192_REG_MODE);
|
|
|
|
static struct attribute *ad7192_attributes[] = {
|
|
&iio_dev_attr_sampling_frequency.dev_attr.attr,
|
|
&iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
|
|
&iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
|
|
&iio_dev_attr_bridge_switch_en.dev_attr.attr,
|
|
&iio_dev_attr_ac_excitation_en.dev_attr.attr,
|
|
NULL
|
|
};
|
|
|
|
static const struct attribute_group ad7192_attribute_group = {
|
|
.attrs = ad7192_attributes,
|
|
};
|
|
|
|
static struct attribute *ad7195_attributes[] = {
|
|
&iio_dev_attr_sampling_frequency.dev_attr.attr,
|
|
&iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
|
|
&iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
|
|
&iio_dev_attr_bridge_switch_en.dev_attr.attr,
|
|
NULL
|
|
};
|
|
|
|
static const struct attribute_group ad7195_attribute_group = {
|
|
.attrs = ad7195_attributes,
|
|
};
|
|
|
|
static int ad7192_read_raw(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan,
|
|
int *val,
|
|
int *val2,
|
|
long m)
|
|
{
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
int ret, smpl = 0;
|
|
bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
|
|
|
|
switch (m) {
|
|
case IIO_CHAN_INFO_RAW:
|
|
mutex_lock(&indio_dev->mlock);
|
|
if (iio_buffer_enabled(indio_dev))
|
|
ret = -EBUSY;
|
|
else
|
|
ret = ad7192_read(st, chan->address,
|
|
chan->scan_type.realbits / 8, &smpl);
|
|
mutex_unlock(&indio_dev->mlock);
|
|
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
*val = (smpl >> chan->scan_type.shift) &
|
|
((1 << (chan->scan_type.realbits)) - 1);
|
|
|
|
switch (chan->type) {
|
|
case IIO_VOLTAGE:
|
|
if (!unipolar)
|
|
*val -= (1 << (chan->scan_type.realbits - 1));
|
|
break;
|
|
case IIO_TEMP:
|
|
*val -= 0x800000;
|
|
*val /= 2815; /* temp Kelvin */
|
|
*val -= 273; /* temp Celsius */
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return IIO_VAL_INT;
|
|
|
|
case IIO_CHAN_INFO_SCALE:
|
|
switch (chan->type) {
|
|
case IIO_VOLTAGE:
|
|
mutex_lock(&indio_dev->mlock);
|
|
*val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
|
|
*val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
|
|
mutex_unlock(&indio_dev->mlock);
|
|
return IIO_VAL_INT_PLUS_NANO;
|
|
case IIO_TEMP:
|
|
*val = 1000;
|
|
return IIO_VAL_INT;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int ad7192_write_raw(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan,
|
|
int val,
|
|
int val2,
|
|
long mask)
|
|
{
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
int ret, i;
|
|
unsigned int tmp;
|
|
|
|
mutex_lock(&indio_dev->mlock);
|
|
if (iio_buffer_enabled(indio_dev)) {
|
|
mutex_unlock(&indio_dev->mlock);
|
|
return -EBUSY;
|
|
}
|
|
|
|
switch (mask) {
|
|
case IIO_CHAN_INFO_SCALE:
|
|
ret = -EINVAL;
|
|
for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
|
|
if (val2 == st->scale_avail[i][1]) {
|
|
tmp = st->conf;
|
|
st->conf &= ~AD7192_CONF_GAIN(-1);
|
|
st->conf |= AD7192_CONF_GAIN(i);
|
|
|
|
if (tmp != st->conf) {
|
|
ad7192_write_reg(st, AD7192_REG_CONF,
|
|
3, st->conf);
|
|
ad7192_calibrate_all(st);
|
|
}
|
|
ret = 0;
|
|
}
|
|
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
mutex_unlock(&indio_dev->mlock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ad7192_validate_trigger(struct iio_dev *indio_dev,
|
|
struct iio_trigger *trig)
|
|
{
|
|
if (indio_dev->trig != trig)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan,
|
|
long mask)
|
|
{
|
|
return IIO_VAL_INT_PLUS_NANO;
|
|
}
|
|
|
|
static const struct iio_info ad7192_info = {
|
|
.read_raw = &ad7192_read_raw,
|
|
.write_raw = &ad7192_write_raw,
|
|
.write_raw_get_fmt = &ad7192_write_raw_get_fmt,
|
|
.attrs = &ad7192_attribute_group,
|
|
.validate_trigger = ad7192_validate_trigger,
|
|
.driver_module = THIS_MODULE,
|
|
};
|
|
|
|
static const struct iio_info ad7195_info = {
|
|
.read_raw = &ad7192_read_raw,
|
|
.write_raw = &ad7192_write_raw,
|
|
.write_raw_get_fmt = &ad7192_write_raw_get_fmt,
|
|
.attrs = &ad7195_attribute_group,
|
|
.validate_trigger = ad7192_validate_trigger,
|
|
.driver_module = THIS_MODULE,
|
|
};
|
|
|
|
#define AD7192_CHAN_DIFF(_chan, _chan2, _name, _address, _si) \
|
|
{ .type = IIO_VOLTAGE, \
|
|
.differential = 1, \
|
|
.indexed = 1, \
|
|
.extend_name = _name, \
|
|
.channel = _chan, \
|
|
.channel2 = _chan2, \
|
|
.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
|
|
IIO_CHAN_INFO_SCALE_SHARED_BIT, \
|
|
.address = _address, \
|
|
.scan_index = _si, \
|
|
.scan_type = IIO_ST('s', 24, 32, 0)}
|
|
|
|
#define AD7192_CHAN(_chan, _address, _si) \
|
|
{ .type = IIO_VOLTAGE, \
|
|
.indexed = 1, \
|
|
.channel = _chan, \
|
|
.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
|
|
IIO_CHAN_INFO_SCALE_SHARED_BIT, \
|
|
.address = _address, \
|
|
.scan_index = _si, \
|
|
.scan_type = IIO_ST('s', 24, 32, 0)}
|
|
|
|
#define AD7192_CHAN_TEMP(_chan, _address, _si) \
|
|
{ .type = IIO_TEMP, \
|
|
.indexed = 1, \
|
|
.channel = _chan, \
|
|
.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
|
|
IIO_CHAN_INFO_SCALE_SEPARATE_BIT, \
|
|
.address = _address, \
|
|
.scan_index = _si, \
|
|
.scan_type = IIO_ST('s', 24, 32, 0)}
|
|
|
|
static struct iio_chan_spec ad7192_channels[] = {
|
|
AD7192_CHAN_DIFF(1, 2, NULL, AD7192_CH_AIN1P_AIN2M, 0),
|
|
AD7192_CHAN_DIFF(3, 4, NULL, AD7192_CH_AIN3P_AIN4M, 1),
|
|
AD7192_CHAN_TEMP(0, AD7192_CH_TEMP, 2),
|
|
AD7192_CHAN_DIFF(2, 2, "shorted", AD7192_CH_AIN2P_AIN2M, 3),
|
|
AD7192_CHAN(1, AD7192_CH_AIN1, 4),
|
|
AD7192_CHAN(2, AD7192_CH_AIN2, 5),
|
|
AD7192_CHAN(3, AD7192_CH_AIN3, 6),
|
|
AD7192_CHAN(4, AD7192_CH_AIN4, 7),
|
|
IIO_CHAN_SOFT_TIMESTAMP(8),
|
|
};
|
|
|
|
static int __devinit ad7192_probe(struct spi_device *spi)
|
|
{
|
|
struct ad7192_platform_data *pdata = spi->dev.platform_data;
|
|
struct ad7192_state *st;
|
|
struct iio_dev *indio_dev;
|
|
int ret, i , voltage_uv = 0;
|
|
|
|
if (!pdata) {
|
|
dev_err(&spi->dev, "no platform data?\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!spi->irq) {
|
|
dev_err(&spi->dev, "no IRQ?\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
indio_dev = iio_device_alloc(sizeof(*st));
|
|
if (indio_dev == NULL)
|
|
return -ENOMEM;
|
|
|
|
st = iio_priv(indio_dev);
|
|
|
|
st->reg = regulator_get(&spi->dev, "vcc");
|
|
if (!IS_ERR(st->reg)) {
|
|
ret = regulator_enable(st->reg);
|
|
if (ret)
|
|
goto error_put_reg;
|
|
|
|
voltage_uv = regulator_get_voltage(st->reg);
|
|
}
|
|
|
|
st->pdata = pdata;
|
|
|
|
if (pdata && pdata->vref_mv)
|
|
st->int_vref_mv = pdata->vref_mv;
|
|
else if (voltage_uv)
|
|
st->int_vref_mv = voltage_uv / 1000;
|
|
else
|
|
dev_warn(&spi->dev, "reference voltage undefined\n");
|
|
|
|
spi_set_drvdata(spi, indio_dev);
|
|
st->spi = spi;
|
|
st->devid = spi_get_device_id(spi)->driver_data;
|
|
indio_dev->dev.parent = &spi->dev;
|
|
indio_dev->name = spi_get_device_id(spi)->name;
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
indio_dev->channels = ad7192_channels;
|
|
indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
|
|
indio_dev->available_scan_masks = st->available_scan_masks;
|
|
if (st->devid == ID_AD7195)
|
|
indio_dev->info = &ad7195_info;
|
|
else
|
|
indio_dev->info = &ad7192_info;
|
|
|
|
for (i = 0; i < indio_dev->num_channels; i++)
|
|
st->available_scan_masks[i] = (1 << i) | (1 <<
|
|
indio_dev->channels[indio_dev->num_channels - 1].
|
|
scan_index);
|
|
|
|
init_waitqueue_head(&st->wq_data_avail);
|
|
|
|
ret = ad7192_register_ring_funcs_and_init(indio_dev);
|
|
if (ret)
|
|
goto error_disable_reg;
|
|
|
|
ret = ad7192_probe_trigger(indio_dev);
|
|
if (ret)
|
|
goto error_ring_cleanup;
|
|
|
|
ret = ad7192_setup(st);
|
|
if (ret)
|
|
goto error_remove_trigger;
|
|
|
|
ret = iio_device_register(indio_dev);
|
|
if (ret < 0)
|
|
goto error_remove_trigger;
|
|
return 0;
|
|
|
|
error_remove_trigger:
|
|
ad7192_remove_trigger(indio_dev);
|
|
error_ring_cleanup:
|
|
ad7192_ring_cleanup(indio_dev);
|
|
error_disable_reg:
|
|
if (!IS_ERR(st->reg))
|
|
regulator_disable(st->reg);
|
|
error_put_reg:
|
|
if (!IS_ERR(st->reg))
|
|
regulator_put(st->reg);
|
|
|
|
iio_device_free(indio_dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ad7192_remove(struct spi_device *spi)
|
|
{
|
|
struct iio_dev *indio_dev = spi_get_drvdata(spi);
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
|
|
iio_device_unregister(indio_dev);
|
|
ad7192_remove_trigger(indio_dev);
|
|
ad7192_ring_cleanup(indio_dev);
|
|
|
|
if (!IS_ERR(st->reg)) {
|
|
regulator_disable(st->reg);
|
|
regulator_put(st->reg);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct spi_device_id ad7192_id[] = {
|
|
{"ad7190", ID_AD7190},
|
|
{"ad7192", ID_AD7192},
|
|
{"ad7195", ID_AD7195},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(spi, ad7192_id);
|
|
|
|
static struct spi_driver ad7192_driver = {
|
|
.driver = {
|
|
.name = "ad7192",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = ad7192_probe,
|
|
.remove = __devexit_p(ad7192_remove),
|
|
.id_table = ad7192_id,
|
|
};
|
|
module_spi_driver(ad7192_driver);
|
|
|
|
MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
|
|
MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7195 ADC");
|
|
MODULE_LICENSE("GPL v2");
|