456c730153
This driver adds support for /dev/watchdog for boards using either the MCP51 or MCP55 chipsets. These are also known as the nForce 430 and nForce 550. This driver is likely to work on other chipsets as well, though those are the only two that have been tested. Signed-off-by: Mike Waychison <mikew@google.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
64 lines
2 KiB
C
64 lines
2 KiB
C
/*
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* nv_tco: TCO timer driver for nVidia chipsets.
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*
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* (c) Copyright 2005 Google Inc., All Rights Reserved.
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*
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* Supported Chipsets:
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* - MCP51/MCP55
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*
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* (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
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* Reserved.
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* http://www.kernelconcepts.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Neither kernel concepts nor Nils Faerber admit liability nor provide
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* warranty for any of this software. This material is provided
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* "AS-IS" and at no charge.
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*
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* (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>
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* developed for
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* Jentro AG, Haar/Munich (Germany)
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*
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* TCO timer driver for NV chipsets
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* based on softdog.c by Alan Cox <alan@redhat.com>
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*/
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/*
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* Some address definitions for the TCO
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*/
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#define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value */
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#define TCO_TMR(base) ((base) + 0x01) /* TCO Timer Initial Value */
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#define TCO_STS(base) ((base) + 0x04) /* TCO Status Register */
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/*
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* TCO Boot Status bit: set on TCO reset, reset by software or standby
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* power-good (survives reboots), unfortunately this bit is never
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* set.
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*/
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# define TCO_STS_BOOT_STS (1 << 9)
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/*
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* first and 2nd timeout status bits, these also survive a warm boot,
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* and they work, so we use them.
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*/
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# define TCO_STS_TCO_INT_STS (1 << 1)
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# define TCO_STS_TCO2TO_STS (1 << 10)
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# define TCO_STS_RESET (TCO_STS_BOOT_STS | TCO_STS_TCO2TO_STS | \
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TCO_STS_TCO_INT_STS)
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#define TCO_CNT(base) ((base) + 0x08) /* TCO Control Register */
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# define TCO_CNT_TCOHALT (1 << 12)
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#define MCP51_SMBUS_SETUP_B 0xe8
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# define MCP51_SMBUS_SETUP_B_TCO_REBOOT (1 << 25)
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/*
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* The SMI_EN register is at the base io address + 0x04,
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* while TCOBASE is + 0x40.
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*/
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#define MCP51_SMI_EN(base) ((base) - 0x40 + 0x04)
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# define MCP51_SMI_EN_TCO ((1 << 4) | (1 << 5))
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