9b1489e989
Removed selection of COMMON_CLKDEV by CONFIG_ARCH_MX5. This is handled in03e09cd890. arch/arm/plat-mxc/iomux-mx1-mx2.c was moved to arch/arm/plat-mxc/iomux-v1.c in5e2e95f520and got bug fixed in5c17ef878f. The bug in arch/arm/plat-mxc/iomux-v1.c isn't present any more sincebac3fcfad5, so arch/arm/plat-mxc/iomux-mx1-mx2.c is simply deleted. Conflicts: arch/arm/plat-mxc/Kconfig arch/arm/plat-mxc/Makefile arch/arm/plat-mxc/iomux-mx1-mx2.c Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
72 lines
1.9 KiB
C
72 lines
1.9 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MXC_IRQS_H__
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#define __ASM_ARCH_MXC_IRQS_H__
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/*
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* SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
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*/
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#ifdef CONFIG_MXC_TZIC
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#define MXC_INTERNAL_IRQS 128
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#else
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#define MXC_INTERNAL_IRQS 64
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#endif
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#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
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/* these are ordered by size to support multi-SoC kernels */
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#if defined CONFIG_ARCH_MX2
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#define MXC_GPIO_IRQS (32 * 6)
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#elif defined CONFIG_ARCH_MX1
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#define MXC_GPIO_IRQS (32 * 4)
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#elif defined CONFIG_ARCH_MX25
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#define MXC_GPIO_IRQS (32 * 4)
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#elif defined CONFIG_ARCH_MX5
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#define MXC_GPIO_IRQS (32 * 4)
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#elif defined CONFIG_ARCH_MXC91231
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#define MXC_GPIO_IRQS (32 * 4)
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#elif defined CONFIG_ARCH_MX3
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#define MXC_GPIO_IRQS (32 * 3)
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#endif
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/*
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* The next 16 interrupts are for board specific purposes. Since
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* the kernel can only run on one machine at a time, we can re-use
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* these. If you need more, increase MXC_BOARD_IRQS, but keep it
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* within sensible limits.
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*/
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#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
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#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
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#define MXC_BOARD_IRQS 80
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#else
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#define MXC_BOARD_IRQS 16
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#endif
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#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
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#ifdef CONFIG_MX3_IPU_IRQS
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#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
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#else
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#define MX3_IPU_IRQS 0
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#endif
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/* REVISIT: Add IPU irqs on IMX51 */
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#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
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extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
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/* all normal IRQs can be FIQs */
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#define FIQ_START 0
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/* switch betwean IRQ and FIQ */
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extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
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#endif /* __ASM_ARCH_MXC_IRQS_H__ */
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