ca5d3f1491
checkpatch.pl --file cleanups:
before:
total: 74 errors, 3 warnings, 386 lines checked
after:
total: 0 errors, 0 warnings, 377 lines checked
no code changed:
arch/x86/lib/mmx_32.o:
text data bss dec hex filename
1323 0 8 1331 533 mmx_32.o.before
1323 0 8 1331 533 mmx_32.o.after
md5:
4cc39f1017dc40a5ebf02ce0ff7312bc mmx_32.o.before.asm
4cc39f1017dc40a5ebf02ce0ff7312bc mmx_32.o.after.asm
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
377 lines
8 KiB
C
377 lines
8 KiB
C
/*
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* MMX 3DNow! library helper functions
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*
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* To do:
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* We can use MMX just for prefetch in IRQ's. This may be a win.
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* (reported so on K6-III)
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* We should use a better code neutral filler for the short jump
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* leal ebx. [ebx] is apparently best for K6-2, but Cyrix ??
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* We also want to clobber the filler register so we don't get any
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* register forwarding stalls on the filler.
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*
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* Add *user handling. Checksums are not a win with MMX on any CPU
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* tested so far for any MMX solution figured.
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*
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* 22/09/2000 - Arjan van de Ven
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* Improved for non-egineering-sample Athlons
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*
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*/
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#include <linux/hardirq.h>
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#include <linux/string.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <asm/i387.h>
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#include <asm/asm.h>
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void *_mmx_memcpy(void *to, const void *from, size_t len)
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{
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void *p;
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int i;
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if (unlikely(in_interrupt()))
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return __memcpy(to, from, len);
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p = to;
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i = len >> 6; /* len/64 */
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kernel_fpu_begin();
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__asm__ __volatile__ (
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"1: prefetch (%0)\n" /* This set is 28 bytes */
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" prefetch 64(%0)\n"
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" prefetch 128(%0)\n"
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" prefetch 192(%0)\n"
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" prefetch 256(%0)\n"
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"2: \n"
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".section .fixup, \"ax\"\n"
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"3: movw $0x1AEB, 1b\n" /* jmp on 26 bytes */
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b)
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: : "r" (from));
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for ( ; i > 5; i--) {
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__asm__ __volatile__ (
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"1: prefetch 320(%0)\n"
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"2: movq (%0), %%mm0\n"
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" movq 8(%0), %%mm1\n"
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" movq 16(%0), %%mm2\n"
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" movq 24(%0), %%mm3\n"
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" movq %%mm0, (%1)\n"
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" movq %%mm1, 8(%1)\n"
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" movq %%mm2, 16(%1)\n"
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" movq %%mm3, 24(%1)\n"
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" movq 32(%0), %%mm0\n"
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" movq 40(%0), %%mm1\n"
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" movq 48(%0), %%mm2\n"
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" movq 56(%0), %%mm3\n"
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" movq %%mm0, 32(%1)\n"
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" movq %%mm1, 40(%1)\n"
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" movq %%mm2, 48(%1)\n"
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" movq %%mm3, 56(%1)\n"
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".section .fixup, \"ax\"\n"
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"3: movw $0x05EB, 1b\n" /* jmp on 5 bytes */
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b)
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: : "r" (from), "r" (to) : "memory");
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from += 64;
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to += 64;
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}
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for ( ; i > 0; i--) {
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__asm__ __volatile__ (
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" movq (%0), %%mm0\n"
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" movq 8(%0), %%mm1\n"
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" movq 16(%0), %%mm2\n"
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" movq 24(%0), %%mm3\n"
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" movq %%mm0, (%1)\n"
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" movq %%mm1, 8(%1)\n"
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" movq %%mm2, 16(%1)\n"
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" movq %%mm3, 24(%1)\n"
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" movq 32(%0), %%mm0\n"
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" movq 40(%0), %%mm1\n"
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" movq 48(%0), %%mm2\n"
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" movq 56(%0), %%mm3\n"
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" movq %%mm0, 32(%1)\n"
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" movq %%mm1, 40(%1)\n"
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" movq %%mm2, 48(%1)\n"
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" movq %%mm3, 56(%1)\n"
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: : "r" (from), "r" (to) : "memory");
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from += 64;
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to += 64;
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}
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/*
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* Now do the tail of the block:
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*/
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__memcpy(to, from, len & 63);
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kernel_fpu_end();
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return p;
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}
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EXPORT_SYMBOL(_mmx_memcpy);
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#ifdef CONFIG_MK7
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/*
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* The K7 has streaming cache bypass load/store. The Cyrix III, K6 and
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* other MMX using processors do not.
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*/
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static void fast_clear_page(void *page)
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{
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int i;
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kernel_fpu_begin();
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__asm__ __volatile__ (
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" pxor %%mm0, %%mm0\n" : :
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);
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for (i = 0; i < 4096/64; i++) {
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__asm__ __volatile__ (
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" movntq %%mm0, (%0)\n"
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" movntq %%mm0, 8(%0)\n"
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" movntq %%mm0, 16(%0)\n"
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" movntq %%mm0, 24(%0)\n"
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" movntq %%mm0, 32(%0)\n"
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" movntq %%mm0, 40(%0)\n"
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" movntq %%mm0, 48(%0)\n"
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" movntq %%mm0, 56(%0)\n"
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: : "r" (page) : "memory");
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page += 64;
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}
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/*
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* Since movntq is weakly-ordered, a "sfence" is needed to become
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* ordered again:
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*/
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__asm__ __volatile__("sfence\n"::);
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kernel_fpu_end();
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}
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static void fast_copy_page(void *to, void *from)
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{
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int i;
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kernel_fpu_begin();
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/*
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* maybe the prefetch stuff can go before the expensive fnsave...
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* but that is for later. -AV
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*/
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__asm__ __volatile__(
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"1: prefetch (%0)\n"
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" prefetch 64(%0)\n"
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" prefetch 128(%0)\n"
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" prefetch 192(%0)\n"
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" prefetch 256(%0)\n"
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"2: \n"
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".section .fixup, \"ax\"\n"
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"3: movw $0x1AEB, 1b\n" /* jmp on 26 bytes */
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b) : : "r" (from));
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for (i = 0; i < (4096-320)/64; i++) {
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__asm__ __volatile__ (
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"1: prefetch 320(%0)\n"
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"2: movq (%0), %%mm0\n"
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" movntq %%mm0, (%1)\n"
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" movq 8(%0), %%mm1\n"
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" movntq %%mm1, 8(%1)\n"
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" movq 16(%0), %%mm2\n"
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" movntq %%mm2, 16(%1)\n"
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" movq 24(%0), %%mm3\n"
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" movntq %%mm3, 24(%1)\n"
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" movq 32(%0), %%mm4\n"
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" movntq %%mm4, 32(%1)\n"
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" movq 40(%0), %%mm5\n"
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" movntq %%mm5, 40(%1)\n"
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" movq 48(%0), %%mm6\n"
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" movntq %%mm6, 48(%1)\n"
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" movq 56(%0), %%mm7\n"
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" movntq %%mm7, 56(%1)\n"
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".section .fixup, \"ax\"\n"
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"3: movw $0x05EB, 1b\n" /* jmp on 5 bytes */
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b) : : "r" (from), "r" (to) : "memory");
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from += 64;
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to += 64;
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}
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for (i = (4096-320)/64; i < 4096/64; i++) {
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__asm__ __volatile__ (
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"2: movq (%0), %%mm0\n"
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" movntq %%mm0, (%1)\n"
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" movq 8(%0), %%mm1\n"
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" movntq %%mm1, 8(%1)\n"
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" movq 16(%0), %%mm2\n"
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" movntq %%mm2, 16(%1)\n"
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" movq 24(%0), %%mm3\n"
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" movntq %%mm3, 24(%1)\n"
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" movq 32(%0), %%mm4\n"
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" movntq %%mm4, 32(%1)\n"
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" movq 40(%0), %%mm5\n"
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" movntq %%mm5, 40(%1)\n"
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" movq 48(%0), %%mm6\n"
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" movntq %%mm6, 48(%1)\n"
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" movq 56(%0), %%mm7\n"
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" movntq %%mm7, 56(%1)\n"
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: : "r" (from), "r" (to) : "memory");
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from += 64;
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to += 64;
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}
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/*
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* Since movntq is weakly-ordered, a "sfence" is needed to become
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* ordered again:
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*/
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__asm__ __volatile__("sfence \n"::);
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kernel_fpu_end();
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}
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#else /* CONFIG_MK7 */
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/*
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* Generic MMX implementation without K7 specific streaming
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*/
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static void fast_clear_page(void *page)
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{
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int i;
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kernel_fpu_begin();
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__asm__ __volatile__ (
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" pxor %%mm0, %%mm0\n" : :
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);
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for (i = 0; i < 4096/128; i++) {
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__asm__ __volatile__ (
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" movq %%mm0, (%0)\n"
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" movq %%mm0, 8(%0)\n"
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" movq %%mm0, 16(%0)\n"
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" movq %%mm0, 24(%0)\n"
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" movq %%mm0, 32(%0)\n"
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" movq %%mm0, 40(%0)\n"
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" movq %%mm0, 48(%0)\n"
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" movq %%mm0, 56(%0)\n"
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" movq %%mm0, 64(%0)\n"
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" movq %%mm0, 72(%0)\n"
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" movq %%mm0, 80(%0)\n"
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" movq %%mm0, 88(%0)\n"
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" movq %%mm0, 96(%0)\n"
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" movq %%mm0, 104(%0)\n"
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" movq %%mm0, 112(%0)\n"
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" movq %%mm0, 120(%0)\n"
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: : "r" (page) : "memory");
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page += 128;
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}
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kernel_fpu_end();
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}
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static void fast_copy_page(void *to, void *from)
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{
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int i;
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kernel_fpu_begin();
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__asm__ __volatile__ (
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"1: prefetch (%0)\n"
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" prefetch 64(%0)\n"
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" prefetch 128(%0)\n"
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" prefetch 192(%0)\n"
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" prefetch 256(%0)\n"
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"2: \n"
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".section .fixup, \"ax\"\n"
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"3: movw $0x1AEB, 1b\n" /* jmp on 26 bytes */
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b) : : "r" (from));
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for (i = 0; i < 4096/64; i++) {
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__asm__ __volatile__ (
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"1: prefetch 320(%0)\n"
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"2: movq (%0), %%mm0\n"
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" movq 8(%0), %%mm1\n"
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" movq 16(%0), %%mm2\n"
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" movq 24(%0), %%mm3\n"
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" movq %%mm0, (%1)\n"
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" movq %%mm1, 8(%1)\n"
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" movq %%mm2, 16(%1)\n"
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" movq %%mm3, 24(%1)\n"
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" movq 32(%0), %%mm0\n"
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" movq 40(%0), %%mm1\n"
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" movq 48(%0), %%mm2\n"
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" movq 56(%0), %%mm3\n"
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" movq %%mm0, 32(%1)\n"
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" movq %%mm1, 40(%1)\n"
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" movq %%mm2, 48(%1)\n"
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" movq %%mm3, 56(%1)\n"
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".section .fixup, \"ax\"\n"
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"3: movw $0x05EB, 1b\n" /* jmp on 5 bytes */
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b)
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: : "r" (from), "r" (to) : "memory");
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from += 64;
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to += 64;
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}
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kernel_fpu_end();
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}
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#endif /* !CONFIG_MK7 */
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/*
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* Favour MMX for page clear and copy:
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*/
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static void slow_zero_page(void *page)
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{
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int d0, d1;
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__asm__ __volatile__(
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"cld\n\t"
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"rep ; stosl"
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: "=&c" (d0), "=&D" (d1)
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:"a" (0), "1" (page), "0" (1024)
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:"memory");
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}
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void mmx_clear_page(void *page)
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{
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if (unlikely(in_interrupt()))
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slow_zero_page(page);
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else
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fast_clear_page(page);
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}
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EXPORT_SYMBOL(mmx_clear_page);
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static void slow_copy_page(void *to, void *from)
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{
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int d0, d1, d2;
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__asm__ __volatile__(
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"cld\n\t"
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"rep ; movsl"
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: "=&c" (d0), "=&D" (d1), "=&S" (d2)
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: "0" (1024), "1" ((long) to), "2" ((long) from)
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: "memory");
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}
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void mmx_copy_page(void *to, void *from)
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{
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if (unlikely(in_interrupt()))
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slow_copy_page(to, from);
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else
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fast_copy_page(to, from);
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}
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EXPORT_SYMBOL(mmx_copy_page);
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